tc59lm818dmg TOSHIBA Semiconductor CORPORATION, tc59lm818dmg Datasheet
tc59lm818dmg
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tc59lm818dmg Summary of contents
Page 1
... TC59LM818DMG can operate fast core cycle compared with regular DDR SDRAM. TC59LM818DMG is suitable for Network, Server and other applications where large memory density and low power consumption are required. The Output Driver for Network FCRAM transfer under light loading condition ...
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... Clock Input Write/Read Data Strobe V Power (+2 Ground SS Power (+1 DDQ (for DQ buffer) Ground V SSQ (for DQ buffer) V Reference Voltage REF NC Not Connected TC59LM818DMG-33,-40 PIN ASSIGNMENT (TOP VIEW) ball pitch=1.0 x 1.0mm x18 Index V DQ17 SS B DQ16 DQ15 V Q ...
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... ADDRESS BUFFER UPPER ADDRESS BA0, BA1 LOWER ADDRESS REFRESH COUNTER BURST COUNTER Note: The TC59LM818DMG configuration is 4 Bank of 32768 × 128 × cell array with the DQ pins numbered DQ0~DQ17. To each block LATCH COLUMN DECODER LATCH WRITE ADDRESS LATCH/ ADDRESS COMPARATOR ...
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... MIN 2.375 1.4 /2 × 95% V DDQ + 0.125 V REF −0.1 −0.1 0.4 + 0.2 V REF −0.1 0.55 /2 − 0.125 V DDQ /2 − 0.125 V DDQ TC59LM818DMG-33,-40 RATING UNIT −0. 0.3 V DDQ + 0 0~85 °C −55~150 °C 260 ° ± 0°C ~ 85°C) ...
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... V with a pulse width ≤ 5 ns. DDQ = −0.7 V with a pulse width ≤ the transmitting device. DDQ ( CLK )} /2 ICK ICK V (min) ISO ISO = 1 MHz 25°C) DDQ PARAMETER TC59LM818DMG-33,-40 (DC ICK ICK (max) MIN MAX Delta 1.5 3.0 0.25 1.5 3 ...
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... IN DDQ = 0mA ; OUT (AC) (min) ≤ V ≤ DDQ interval ; REFC (AC) (min) ≤ V ≤ DDQ REFC /2), DDQ /2) DDQ and TC59LM818DMG-33,-40 MAX UNIT -33 -40 235 210 450 400 450 400 235 210 , 15 15 2005-10-19 6/57 NOTES ...
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... 1.420 0.280 – 0.4V OH DDQ = 0. – 0.4V OH DDQ = 1.4V~1.6V Not defined Not defined TC59LM818DMG-33,-40 MIN MAX UNIT NOTES −5 µA 5 −5 µA 5 −5 µA 5 −5.6 5.6 −9.8 9.8 −2.8 2.8 −4 ...
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... C 0.8 L 0.45 × t C 0.8 L 0.35 0.35 0.6 0.6 −0.5 0.5 TC59LM818DMG-33,-40 (Notes -40 UNIT NOTES MIN MAX 25 5.0 7.5 4.5 7.5 4.0 7.5 25 0.45 × t CK 0.45 × t CK −0.6 0 0.3 −0.65 0. −0.65 0.65 min ...
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... I REFC 200 TC59LM818DMG-33,-40 (Notes (continued) -40 UNIT NOTES MIN MAX 0 0.7 ns 0.1 1 −0.5 × 0.4 3.9 µs 200 5 6 ...
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... V IH min IL max contains more than one decimal place, the result 3.3 ns, 0.8 × rounded up to 2.7 ns.) /2 ± 0.1 V from steady state. DDQ = minimum ∼6.0ns. When t CK (MIN/MAX) = −0.65ns / 0.65ns AC TC59LM818DMG-33,-40 VALUE UNIT + 0 REF − 0 REF V ...
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... V (TYP) DDQ PDEX l RSC l PDA DESL RDA MRS DESL RDA MRS op-code op-code EMRS MRS EMRS TC59LM818DMG-33,- RSC REFC l = 200clock cycle(min) LOCK DESL WRA REF DESL WRA REF MRS Auto Refresh cycle 2005-10-19 11/57 l REFC DESL Low Normal Operation ...
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... 1st 2nd UA TC59LM818DMG-33,- Refer to the Command Truth Table (AC (AC (AC Rev 1.4 2005-10-19 12/57 ...
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... CAS latency = 4 QS Low (output) DQ Hi-Z (output) CAS latency = 5 QS Low (output) DQ Hi-Z (output) CAS latency = 6 QS Low (output) DQ Hi-Z (output) Note: DQ0 to DQ17 are aligned with QS. TC59LM818DMG-33,-40 DESL t t CKQS CKQS QSP QSP CKQS QSQV LZ QSQ QSQ QSQ ...
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... CAS latency = 4 QS (output) DQ Hi-Z (output) CAS latency = 5 QS (output) DQ Hi-Z (output) CAS latency = 6 QS (output) DQ Hi-Z (output) Note: DQ0 to DQ17 are aligned with QS always asserted in Free Running QS mode. TC59LM818DMG-33,-40 DESL t t CKQS CKQS CKQS QSP QSP QSQV QSQ ...
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... DQSS t DSPRES t DSP t DSPREH Preamble t DSPRE DQSS DQSS t DSPRES t DSPREH Preamble t DSPRE t DQSS Low TC59LM818DMG-33,-40 t DSPSTH t DSS t DSPST Postamble DSS t t DSPSTH DSS DSP DSP DSPST Postamble ...
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... I Timing REFI PAUSE XXXX CLK CLK Input (control & addresses) Command Note: “I ” means “I XXXX REFI PAUSE XXXX ”, “I ”, “I ”, etc. RCD RAS TC59LM818DMG-33,- Command Rev 1.4 2005-10-19 16/57 ...
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... BA1~ FN A14 A13 BA0 × × VW0 VW1 VW0 VW1 × L × TC59LM818DMG-33,-40 A14~ × × × A12~ A10~ A11 × × × × × × × × ...
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... CURRENT CS FN STATE n − × Standby Power × × Down Power × Down from REF command. FPDL TC59LM818DMG-33,- A6~A0 × × × BA1~BA0 A14~ A6~A0 NOTES × × × × × × × × × × ...
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... H SELFX × × L TC59LM818DMG-33,-40 ACTION NOP Row activate for Read Row activate for Write Power Down Entry Illegal Refer to Power Down State Begin Read Illegal Invalid Begin Write Auto-Refresh Illegal Self-Refresh Entry ...
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... Reserved Reserved *4 *4 BA0 A14~ TC59LM818DMG-33,- A6~ BURST TYPE (BT) 0 Sequential 1 Interleave A1 A0 BURST LENGTH (BL Reserved Reserved × × A6~A5 A4~A3 ...
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... STANDBY (IDLE) WRA RDA ACTIVE ACTIVE (RESTORE) LAL WRITE READ (BUFFER) TC59LM818DMG-33,-40 POWER DOWN PDEN ( MODE REGISTER MRS LAL Command input Automatic return The second command at Active state must be issued 1 clock after RDA or WRA command input. 2005-10-19 21/57 ...
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... I RC RDA LAL DESL = 4 cycles =1 cycle = 4 cycles I I RCD RAS TC59LM818DMG-33,- cycles I RC RDA LAL DESL =1 cycle = 4 cycles I I RCD RAS ...
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... Hi-Z (output cycles I RC DESL RDA LAL = 5 cycles =1 cycle I RCD TC59LM818DMG-33,- DESL RDA LAL = 5 cycles =1 cycle I I RAS RCD ...
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... DESL RDA LAL = 6 cycles =1 cycle I RCD TC59LM818DMG-33,- cycles I RC DESL RDA = 6 cycles I I RAS RCD Rev 1 ...
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... I RC WRA LAL DESL = 4 cycles =1 cycle = 4 cycles I I RCD RAS TC59LM818DMG-33,- cycles I RC WRA LAL DESL =1 cycle = 4 cycles I I RCD RAS ...
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... DESL WRA LAL = 5 cycles =1 cycle I RCD TC59LM818DMG-33,- cycles I RC DESL WRA LAL = 5 cycles =1 cycle I I RAS RCD ...
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... (input DESL WRA LAL = 6 cycles =1 cycle I I RAS RCD TC59LM818DMG-33,- cycles I RC DESL WRA = 6 cycles I I RAS RCD Rev 1 ...
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... I RC WRA LAL DESL Read data TC59LM818DMG-33,- cycles I RC RDA LAL DESL ...
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... QS (output Hi DESL WRA LAL Read data TC59LM818DMG-33,- cycles DESL RDA LAL Write data 2005-10-19 29/57 15 DESL Rev 1 ...
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... DQ Hi-Z (output DESL WRA LAL Read data TC59LM818DMG-33,- cycles I RC DESL RDA Write data Rev 1.4 ...
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... LAL RDA LAL Bank Bank "a" "b" (Bank"b" cycles Qa0Qa1 Qb0Qb1 Qa0Qa1Qa2Qa3Qb0Qb1Qb2Qb3 Qa0Qa1 Qb0Qb1 Qa0Qa1Qa2Qa3Qb0Qb1Qb2Qb3 TC59LM818DMG-33,- cycles = 2 cycles I RBD RBD RDA LAL RDA LAL RDA LAL ...
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... RDA Bank Bank "a" "b" (Bank"b" cycles Qa0Qa1 Qb0Qb1 Qa0Qa1Qa2Qa3Qb0Qb1Qb2Qb3 Qa0Qa1 Qb0Qb1 Qa0Qa1Qa2Qa3Qb0Qb1Qb2Qb3 TC59LM818DMG-33,- cycles cycles cycles RBD RBD LAL RDA LAL RDA LAL RDA ...
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... RDA UA LA Bank Bank "a" (Bank"b" cycles Qa0Qa1 Qa0Qa1Qa2Qa3Qb0Qb1Qb2Qb3 Qa0Qa1 Qa0Qa1Qa2Qa3Qb0Qb1Qb2Qb3 TC59LM818DMG-33,- cycles cycles cycles RBD RBD RBD LAL RDA LAL RDA LAL ...
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... UA LA Bank Bank "a" "b" (Bank"b" cycles Da0 Da1 Db0Db1 Da0 Da1 Da2Da3Db0Db1Db2Db3 Da0 Da1 Db0Db1 Da0 Da1 Da2Da3Db0Db1Db2Db3 TC59LM818DMG-33,- cycles cycles RBD RBD WRA LAL WRA LAL WRA LAL UA ...
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... WRA Bank Bank "a" "b" (Bank"b" cycles Da0Da1 Db0Db1 Da0Da1Da2Da3Db0Db1Db2Db3 Da0Da1 Db0Db1 Da0Da1Da2Da3Db0Db1Db2Db3 TC59LM818DMG-33,- cycles cycles cycles RBD RBD LAL WRA LAL WRA LAL WRA ...
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... I I RBD WRA LAL DESL UA LA Bank "a" (Bank"b" cycles Da0Da1 Db0Db1 Da0Da1Da2Da3Db0Db1Db2Db3 Da0Da1 Db0Db1 Da0Da1Da2Da3Db0Db1Db2Db3 TC59LM818DMG-33,- cycles cycles I RBD RBD RBD WRA LAL WRA LAL WRA LAL ...
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... Da0 Da1 Qb0 Qb1 Da0 Da1 Qb0 Qb1 Da0 Da1 Da0 Da1 Qb0 Qb1 Da0 Da1 Qb0 Qb1 Da0 Da1 TC59LM818DMG-33,- DESL WRA LAL RDA LAL DESL = 2 cycles ...
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... Da0 Da1 Da2 Da3 Qb0 Qb1 Da0 Da1 Da2 Da3 Da0 Da1 Da2 Da3 Qb0 Qb1 Qb2 Qb3 Da0 Da1 Da2 Da3 Qb0 Qb1 Da0 Da1 Da2 Da3 TC59LM818DMG-33,- DESL LAL WRA LAL = 3 cycles = 1 cycle I ...
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... Bank "a" WRA LAL DESL LA=#1 UA VW=1 VW0 = High VW1 = High Bank "a" Last three data are masked. TC59LM818DMG-33,- DESL D0 #1 (#0) Last one data is masked. WRA LAL DESL LA=#2 UA VW=2 VW0 = Low VW1 = High Bank " ...
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... When PD is brought to "High", a valid executable command may be applied DESL QPDH Power Down Entry (max.) to maintain the data written into cell. REFI TC59LM818DMG-33,- n-2 n-1 n n+1 DESL = 2 cycle , t l RC(min) REFI(max) Hi-Z Hi-Z Power Down Exit cycles later. PDA 2005-10-19 40/57 n+2 I PDA RDA ...
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... When PD is brought to "High", a valid executable command may be applied DESL QPDH (max.) to maintain the data written into cell. REFI TC59LM818DMG-33,- n-2 n-1 n n+1 DESL = 2 cycle , t l RC(min) REFI(max) cycles later. PDA 2005-10-19 41/57 n+2 I PDA RDA ...
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... QS (output) DQ (output) Note: Minimum delay from LAL following RDA to RDA of MRS operation is CL+BL/ DESL RDA MRS Valid (opcode) BA0="0" BA1="0" TC59LM818DMG-33,- cycles I RSC RDA DESL or WRA UA BA Rev 1.4 2005-10-19 42/57 15 LAL ...
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... DQ (input) Note: Minimum delay from LAL following WRA to RDA of MRS operation is WL+BL/ DESL RDA MRS Valid (opcode) BA0="0" BA1="0" TC59LM818DMG-33,- cycles I RSC RDA DESL or WRA UA BA Rev 1.4 2005-10-19 43/57 ...
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... DLL switch in Extended Mode Register must be set to enable mode for normal operation. DLL lock-on time is needed after initial EMRS operation. See Power Up Sequence DESL RDA MRS Valid (opcode) BA0="1" BA1="0" TC59LM818DMG-33,- cycles I RSC RDA DESL or WRA UA BA period ...
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... DLL lock-on time is needed after initial EMRS operation. See Power Up Sequence. Minimum delay from LAL following WRA to RDA of EMRS operation is WL+BL/ DESL RDA MRS Valid (opcode) BA0="1" BA1="0" TC59LM818DMG-33,- cycles I RSC RDA DESL or WRA UA BA period ...
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... I I RAS RCD must be meet 19 clock cycles. REFC must be satisfied. REFI WRA REF 8 Refresh cycle TC59LM818DMG-33,-40 n − cycles I REFC RDA LAL or DESL or MRS or WRA Low Hi cycles I REFC RDA LAL or DESL or ...
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... RCD I LOCK after PD is brought to “High”. REFC LOCK TC59LM818DMG-33,- Hi-Z (min) and t (max) to Self FPDL FPDL , TC59LM818DMG perform Auto Refresh PDV (max) and l , TC59LM818DMG FPDL PDV from REF command even though − − Command (1st) *5 Command (2nd) ...
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... I LOCK after PD is brought to “High”. REFC LOCK TC59LM818DMG-33,- Hi-Z Hi-Z (min) and t (max) to Self FPDL FPDL , TC59LM818DMG perform Auto Refresh PDV (max) and l , TC59LM818DMG FPDL PDV from REF command even though − − Command (1st) *5 Command (2nd) ...
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... LAL command. The A0 to A14 inputs are also used for setting the data in the Regular or Extended Mode Register set cycle. I/O Organization CS & FN BA0 Bank #0 0 Bank #1 1 Bank #2 0 Bank #3 1 UPPER ADDRESS 18 bits A0~A14 TC59LM818DMG-33,-40 BA1 LOWER ADDRESS A0~A6 2005-10-19 49/ Each Rev 1.4 ...
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... V DD DDQ V and V are power supply pins for memory core and peripheral circuits and V are power supply pins for the output buffer. DDQ SSQ REFERENCE VOLTAGE: V REF V is reference voltage for all input signals. REF , SSQ TC59LM818DMG-33,-40 Rev 1.4 2005-10-19 50/57 ...
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... PD Power Down Mode ( When all banks are in the idle state and DQ outputs are in Hi-Z states, the TC59LM818DMG become Power Down Mode by asserting PD is “Low”. When the device enters the Power Down Mode, all input and output buffers are disabled after specified time except for PD , CLK, CLK and QS. Therefore, the power dissipation lowers. To exit the Power Down Mode, PD has to be brought to “ ...
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... RDA command instead of the LAL command. The data to be set in the Mode Register is transferred using A0 to A14, BA0 and BA1 address inputs. The TC59LM818DMG have two mode registers. These are Regular and Extended Mode Register. The Regular or Extended Mode Register is chosen by BA0 and BA1 in the MRS command ...
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... LA1~LA2 ACCESS ADDRESS CAS LATENCY 0 0 Reserved 0 1 Reserved 1 0 Reserved 1 1 Reserved Reserved TC59LM818DMG-33,-40 Data Data Data Data BURST LENGTH 2 words 4 words Rev 1.4 2005-10-19 53/57 ...
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... These bits are reserved for future operations and must be set to “0” for normal operation. DQ OUTPUT DRIVER IMPEDANCE CONTROL Normal Output Driver 0 1 Strong Output Driver 1 0 Weak Output Driver 1 1 Reserved A5 STROBE SELECT 0 Reserved 1 Reserved 0 Unidirectional DS/QS mode 1 Unidirectional DS/Free running QS mode TC59LM818DMG-33,-40 Rev 1.4 2005-10-19 54/57 ...
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... PACKAGE DIMENSIONS P-BGA60-0917-1.00AZ Weight: 0.15 g (typ.) TC59LM818DMG-33,-40 16.5 0 12.518 -0.15 0.2 S 0.5 0.05 0. 1.25 Rev 1.4 2005-10-19 55/57 ...
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... Rev.1.2 (Mar. 7 ’2005) Corrected figure of l based AC timing spec table ( page 11, 40, 41, 47 PDA − Rev.1.3 (Sep. 26 ’2005) IDD6( Self-Refresh current ) spec changed from 10mA to 15mA ( page 1 and 6 ). − Rev.1.4 (Oct.19 ’2005) “-30”( 333MHz clock/666Mbps ) version dropped. TC59LM818DMG-33,-40 Rev 1.4 2005-10-19 56/57 ...
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... The products described in this document are subject to the foreign exchange and foreign trade laws. • TOSHIBA products should not be embedded to the downstream products which are prohibited to be produced and sold, under any law and regulations. TC59LM818DMG-33,-40 030619EBA Rev 1.4 2005-10-19 57/57 ...