tc59lm818dmg TOSHIBA Semiconductor CORPORATION, tc59lm818dmg Datasheet - Page 11

• Manufacturer Part Number: tc59lm818dmg
• Description: 288mbits Network Fcram2 ? 4,194,304-words ? 4 Banks ? 18-bits
• Manufacturer: TOSHIBA Semiconductor CORPORATION

(Free Running mode)
(Uni-QS mode)
Command
Address
POWER UP SEQUENCE
NOTES:
(Input)
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
V
V
QS
CLK
V
DDQ
CLK
QS
REF
DQ
DS
PD
DD
(1)
(2)
(3)
As for PD , being maintained by the low state (≤ 0.2 V) is desirable before a power-supply injection.
Apply V
Apply V
Start clock (CLK, CLK ) and maintain stable condition for 200 µs (min).
After stable power and clock, apply DESL and take PD =H.
Issue EMRS to enable DLL and to define driver strength and data strobe type. (Note: 1)
Issue MRS for set CAS latency (CL), Burst Type (BT), and Burst Length (BL). (Note: 1)
Issue two or more Auto-Refresh commands (Note: 1).
Ready for normal operation after 200 clocks from Extended Mode Register programming.
Sequence 6, 7 and 8 can be issued in random order.
L = Logic Low, H = Logic High
DQ output is Hi-Z state during power upsequence.
DD
DDQ
before or at the same time as V
before or at the same time as V
200us(min)
t
PDEX
DESL
1.5V or 1.8V(TYP)
1/2 V
2.5V(TYP)
DDQ
RDA MRS DESL
EMRS
(TYP)
op-code
l
PDA
EMRS
l
RSC
DDQ
REF
.
RDA MRS
.
MRS
op-code
MRS
l
DESL WRA REF
RSC
l
LOCK
= 200clock cycle(min)
TC59LM818DMG-33,-40
DESL
l
REFC
Auto Refresh cycle
WRA REF
2005-10-19 11/57
DESL
l
REFC
Normal Operation
Rev 1.4
Low