tc59lm818dmg TOSHIBA Semiconductor CORPORATION, tc59lm818dmg Datasheet - Page 49

• Manufacturer Part Number: tc59lm818dmg
• Description: 288mbits Network Fcram2 ? 4,194,304-words ? 4 Banks ? 18-bits
• Manufacturer: TOSHIBA Semiconductor CORPORATION

FUNCTIONAL DESCRIPTION
Network FCRAM
transfer.
PIN FUNCTIONS
The FCRAM
The Network FCRAM
CLOCK INPUTS: CLK &
The CS , FN and all address input signals are sampled on the crossing of the positive edge of CLK and the
negative edge of CLK . The QS and DQ output data are aligned to the crossing point of CLK and CLK . The
timing reference point for the differential clock is when the CLK and CLK signals cross during a transition.
POWER DOWN:
Clock Suspend function like a CKE input of a standard SDRAMs, therefore it is illegal to bring PD pin into
low state if any Read or Write operation is being performed.
CHIP SELECT & FUNCTION CONTROL:
operation mode is decided by the combination of the two consecutive operation commands using the CS and
FN inputs.
BANK ADDRESSES: BA0 & BA1
the bank to be used for the operation. BA0 and BA1 also define which mode register is loaded during the Mode
Register Set command (MRS or EMRS).
ADDRESS INPUTS: A0~A14
Upper Addresses with Bank addresses are latched at the RDA or WRA command and the Lower Addresses are
latched at the LAL command. The A0 to A14 inputs are also used for setting the data in the Regular or
Extended Mode Register set cycle.
The CLK and CLK inputs are used as the reference for synchronous operation. CLK is master clock input.
The PD input controls the entry to the Power Down or Self-Refresh modes. The PD input does not have a
The CS and FN inputs are a control signal for forming the operation commands on FCRAM
The BA0 and BA1 inputs are latched at the time of assertion of the RDA or WRA command and are selected
Address inputs are used to access the arbitrary address of the memory cell array within each bank. The
TM
is an acronym of Fast Cycle Random Access Memory.
TM
TM
PD
is competent to perform fast random core access, low latency and high-speed data
I/O Organization
CLK
Bank #0
Bank #1
Bank #2
Bank #3
18 bits
UPPER ADDRESS
CS
A0~A14
BA0
0
1
0
1
& FN
LOWER ADDRESS
A0~A6
BA1
0
0
1
1
TC59LM818DMG-33,-40
2005-10-19 49/57
Rev 1.4
TM
. Each