xr16v2652il32 Exar Corporation, xr16v2652il32 Datasheet - Page 22

• Manufacturer Part Number: xr16v2652il32
• Description: High Performance Duart With 32-byte Fifo
• Manufacturer: Exar Corporation

XR16V2652
HIGH PERFORMANCE DUART WITH 32-BYTE FIFO
.
A
A2-A0
DDRESS
0 1 0
0 0 0
0 0 0
0 0 1
0 1 0
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
0 0 0
0 0 1
0 1 0
T
ABLE
N
MCR
MSR
RHR
DLM
THR
FCR
LCR
SPR
AFR
DLD
R
LSR
DLL
IER
ISR
AME
EG
9: INTERNAL REGISTERS DESCRIPTION.
RD/WR
RD/WR Divisor
RD/WR
RD/WR
RD/WR
RD/WR
RD/WR
RD/WR
R
W
WR
WR
RD
RD
RD
RD
EAD
RITE
/
RX FIFO
RX FIFO
CTS Int.
Enabled
Enable
Trigger
Enable
Global
FIFOs
Pres-
B
Rsvd
BRG
caler
Error
Input
Bit-7
Bit-7
CD#
Bit-7
Bit-7
Bit-7
IT
0/
0/
0
-7
RX FIFO
IR Mode
RTS Int.
Enabled
ENable
Trigger
Enable
Set TX
THR &
FIFOs
Empty
Break
B
Input
Rsvd
Bit-6
Bit-6
Bit-6
Bit-6
Bit-6
TSR
RI#
IT
0/
0/
0
-6
16C550 Compatible Registers
Baud Rate Generator Divisor
4X Mode 8X Mode
TX FIFO
XonAny
Xoff Int.
Enable
Source
Trigger
Empty
DSR#
Parity
B
Rsvd
Input
Bit-5
Bit-5
Bit-5
THR
Bit-5
Bit-5
Bit-5
INT
Set
IT
0/
0/
0/
0/
-5
22
TX FIFO
Lopback
Internal
Source
Trigger
Enable
Enable
Break
Sleep
Mode
Parity
CTS#
B
Even
Input
Rsvd
Bit-4
Bit-4
Bit-4
Bit-4
Bit-4
Bit-4
INT
RX
IT
0/
0/
0/
-4
S
HADED BITS ARE ENABLED WHEN
Stat. Int.
Framing
Modem
Source
Control
Enable
Enable
Enable
Output
Mode
Parity
OP2#
B
Delta
DMA
Error
Rsvd
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
CD#
INT
RX
IT
-3
RX Line
Enable
Source
RXRDY#
Reset
OP1#
Parity
Invert
B
FIFO
Delta
Error
Select
Bit-2
Bit-2
Stat.
Bit-2
Stop
Bit-2
Bit-2
Bit-2
Bit-2
INT
Bits
RI#
Int.
RX
TX
IT
IR
-2
Baudout#
Enable
Source
Control
Length
Output
Empty
Reset
DSR#
RTS#
Over-
B
FIFO
Word
Delta
Error
Select
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
INT
RX
RX
run
TX
Int
IT
-1
rent Write
Source
Control
EFR B
Enable
Enable
Length
Output
Ready
FIFOs
Concur-
DTR#
CTS#
B
Word
Delta
Bit-0
Bit-0
Data
Bit-0
Bit-0
Data
Bit-0
Bit-0
Bit-0
Bit-0
INT
RX
Int.
RX
IT
-0
IT
-4=1
LCR ≠ 0xBF
LCR ≠ 0xBF
LCR ≠ 0xBF
LCR ≠ 0xBF
LCR ≠ 0xBF
EFR[4] = 0
EFR[4] = 1
C
LCR[7]=0
LCR[7]=1
LCR[7]=1
LCR[7]=1
REV. 1.0.2
OMMENT