xr16v2652il32 Exar Corporation, xr16v2652il32 Datasheet - Page 8

• Manufacturer Part Number: xr16v2652il32
• Description: High Performance Duart With 32-byte Fifo
• Manufacturer: Exar Corporation

XR16V2652
HIGH PERFORMANCE DUART WITH 32-BYTE FIFO
Each UART channel in the V2652 has a set of enhanced registers for controlling, monitoring and data loading
and unloading. The configuration register set is compatible to those already available in the standard single
16C550 and dual ST16C2550. These registers function as data holding registers (THR/RHR), interrupt status
and control registers (ISR/IER), a FIFO control register (FCR), receive line status and control registers (LSR/
LCR), modem status and control registers (MSR/MCR), programmable data rate (clock) divisor registers (DLL/
DLM/DLD), and a user accessible Scratchpad Register (SPR).
Beyond the general 16C2550 features and capabilities, the V2652 offers enhanced feature registers (EFR,
Xon/Xoff 1, Xon/Xoff 2) that provide automatic RTS and CTS hardware flow control and Xon/Xoff software flow
control. All the register functions are discussed in full detail later in
REGISTERS” on page
The device does not support direct memory access. The DMA Mode (a legacy term) in this document does not
mean “direct memory access” but refers to data block transfer operation. The DMA mode affects the state of
the RXRDY# A/B and TXRDY# A/B output pins. The transmit and receive FIFO trigger levels provide additional
flexibility to the user for block mode operation. The LSR bits 5-6 provide an indication when the transmitter is
empty or has an empty location(s) for more data. The user can optionally operate the transmit and receive
FIFO in the DMA mode (FCR bit-3=1). When the transmit and receive FIFO are enabled and the DMA mode is
disabled (FCR bit-3 = 0), the V2652 is placed in single-character mode for data transmit or receive operation.
When DMA mode is enabled (FCR bit-3 = 1), the user takes advantage of block mode operation by loading or
unloading the FIFO in a block sequence determined by the selected trigger level. In this mode, the V2652 sets
the TXRDY# pin when the transmit FIFO becomes full, and sets the RXRDY# pin when the receive FIFO
becomes empty. The following table shows their behavior. Also see
2.6
2.7
RXRDY# A/B LOW = 1 byte.
TXRDY# A/B LOW = THR empty.
P
INS
Channel A and B Internal Registers
DMA Mode
HIGH = no data.
HIGH = byte in THR.
(FIFO D
FCR
T
ABLE
BIT
21.
ISABLED
-0=0
2: TXRDY#
)
CS#
1
0
0
LOW = at least 1 byte in FIFO.
HIGH = FIFO empty.
LOW = FIFO empty.
HIGH = at least 1 byte in FIFO.
T
ABLE
(DMA Mode Disabled)
AND
CHSEL
FCR Bit-3 = 0
1: C
RXRDY# O
X
1
0
HANNEL
8
A
UTPUTS IN
AND
Channel A selected
Channel B selected
FCR B
UART de-selected
B S
F
UNCTION
IT
HIGH to LOW transition when FIFO reaches the
trigger level, or time-out occurs.
LOW to HIGH transition when FIFO empties.
LOW = FIFO has at least 1 empty location.
HIGH = FIFO is full.
-0=1 (FIFO E
FIFO
ELECT
Figures 17
AND
“Section 3.0, UART INTERNAL
DMA M
(DMA Mode Enabled)
NABLED
through 22.
FCR Bit-3 = 1
ODE
)
REV. 1.0.2