xr16v2652il32 Exar Corporation, xr16v2652il32 Datasheet - Page 23

• Manufacturer Part Number: xr16v2652il32
• Description: High Performance Duart With 32-byte Fifo
• Manufacturer: Exar Corporation

REV. 1.0.2
SEE”RECEIVER” ON PAGE 13.
SEE”TRANSMITTER” ON PAGE 12.
The Interrupt Enable Register (IER) masks the interrupts from receive data ready, transmit empty, line status
and modem status registers. These interrupts are reported in the Interrupt Status Register (ISR).
When the receive FIFO (FCR BIT-0 = 1) and receive interrupts (IER BIT-0 = 1) are enabled, the RHR interrupts
(see ISR bits 2 and 3) status will reflect the following:
A. The receive data available interrupts are issued to the host when the FIFO has reached the programmed
B. FIFO level will be reflected in the ISR register when the FIFO trigger level is reached. Both the ISR register
C. The receive data ready bit (LSR BIT-0) is set as soon as a character is transferred from the shift register to
4.0 INTERNAL REGISTER DESCRIPTIONS
4.1
4.2
4.3
4.3.1
A
A2-A0
DDRESS
0 0 0
0 0 1
0 1 0
1 0 0
1 0 1
1 1 0
1 1 1
trigger level. It will be cleared when the FIFO drops below the programmed trigger level.
status bit and the interrupt will be cleared when the FIFO drops below the trigger level.
the receive FIFO. It is reset when the FIFO is empty.
T
Receive Holding Register (RHR) - Read- Only
Transmit Holding Register (THR) - Write-Only
Interrupt Enable Register (IER) - Read/Write
ABLE
IER versus Receive FIFO Interrupt Mode Operation
XOFF1 RD/WR
XOFF2 RD/WR
DREV
XON1 RD/WR
XON2 RD/WR
N
DVID
EFR
R
AME
EG
9: INTERNAL REGISTERS DESCRIPTION.
RD/WR
W
R
RD
RD
EAD
RITE
/
Enable
B
Bit-7
Auto
CTS
Bit-7
Bit-7
Bit-7
Bit-7
IT
0
-7
Enable
B
Bit-6
Auto
Bit-6
Bit-6
Bit-6
Bit-6
RTS
IT
0
-6
Enhanced Registers
Special
Select
B
Char
Bit-5
Bit-5
Bit-5
Bit-5
Bit-5
IT
0
-5
23
HIGH PERFORMANCE DUART WITH 32-BYTE FIFO
MCR[7:5],
IER [7:4],
ISR [5:4],
FCR[5:4],
Enable
B
Bit-4
Bit-4
Bit-4
Bit-4
Bit-4
DLD
IT
0
-4
S
HADED BITS ARE ENABLED WHEN
B
Bit-3
Soft-
ware
Flow
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
Cntl
IT
0
-3
B
ware
Bit-2
Soft-
Flow
Bit-2
Bit-2
Bit-2
Bit-2
Bit-2
Cntl
IT
1
-2
B
ware
Bit-1
Soft-
Flow
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Cntl
IT
1
-1
EFR B
B
Bit-0
Soft-
ware
Flow
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
Cntl
IT
0
XR16V2652
-0
IT
-4=1
LCR ≠ 0xBF
LCR=0
DLM=0x00
DLL=0x00
C
LCR[7]=1
OMMENT
X
BF