xr16v2652il32 Exar Corporation, xr16v2652il32 Datasheet - Page 32

• Manufacturer Part Number: xr16v2652il32
• Description: High Performance Duart With 32-byte Fifo
• Manufacturer: Exar Corporation

XR16V2652
HIGH PERFORMANCE DUART WITH 32-BYTE FIFO
MSR[3]: Delta CD# Input Flag
•
•
MSR[4]: CTS Input Status
CTS# pin may function as automatic hardware flow control signal input if it is enabled and selected by Auto
CTS (EFR bit-7). Auto CTS flow control allows starting and stopping of local data transmissions based on the
modem CTS# signal. A HIGH on the CTS# pin will stop UART transmitter as soon as the current character has
finished transmission, and a LOW will resume data transmission. Normally MSR bit-4 bit is the complement of
the CTS# input. However in the loopback mode, this bit is equivalent to the RTS# bit in the MCR register. The
CTS# input may be used as a general purpose input when the modem interface is not used.
MSR[5]: DSR Input Status
Normally this bit is the complement of the DSR# input. In the loopback mode, this bit is equivalent to the DTR#
bit in the MCR register. The DSR# input may be used as a general purpose input when the modem interface is
not used.
MSR[6]: RI Input Status
Normally this bit is the complement of the RI# input. In the loopback mode this bit is equivalent to bit-2 in the
MCR register. The RI# input may be used as a general purpose input when the modem interface is not used.
MSR[7]: CD Input Status
Normally this bit is the complement of the CD# input. In the loopback mode this bit is equivalent to bit-3 in the
MCR register. The CD# input may be used as a general purpose input when the modem interface is not used.
This is a 8-bit general purpose register for the user to store temporary data. The content of this register is
preserved during sleep mode but becomes 0xFF (default) after a reset or a power off-on cycle.
These registers make-up the value of the baud rate divisor. The concatenation of the contents of DLM and
DLL is a 16-bit value is then added to DLD[3:0]/16 to achieve the fractional baud rate divisor. DLD must be
enabled via EFR bit-4 before it can be accessed.
FRACTIONAL DIVISOR” ON PAGE 10.
DLD[5:4]: Sampling Rate Select
These bits select the data sampling rate. By default, the data sampling rate is 16X. The maximum data rate will
double if the 8X mode is selected and will quadruple if the 4X mode is selected. See Table below.
DLD[7:6]: Reserved
This register is used to select specific modes of MF# operation and to allow both UART register sets to be
written concurrently.
4.10
4.11
4.12
Logic 0 = No change on CD# input (default).
Logic 1 = Indicates that the CD# input has changed state since the last time it was monitored. A modem
status interrupt will be generated if MSR interrupt is enabled (IER bit-3).
Scratch Pad Register (SPR) - Read/Write
Baud Rate Generator Registers (DLL, DLM and DLD) - Read/Write
Alternate Function Register (AFR) - Read/Write
DLD[5]
0
0
1
T
ABLE
13: S
SEE”PROGRAMMABLE BAUD RATE GENERATOR WITH
AMPLING
DLD[4]
32
X
0
1
R
ATE
S
ELECT
S
AMPLING
16X
8X
4X
R
ATE
REV. 1.0.2