xr16l2552im Exar Corporation, xr16l2552im Datasheet - Page 27

• Manufacturer Part Number: xr16l2552im
• Description: Industry Smallest Package Uart With 2.25v To 5.5v Operation
• Manufacturer: Exar Corporation

xr
REV. 1.1.1
FCR[2]: TX FIFO Reset
This bit is only active when FCR bit-0 is a ‘1’.
•
•
FCR[3]: DMA Mode Select
Controls the behavior of the TXRDY# and RXRDY# pins. See DMA operation section for details.
•
•
FCR[5:4]: Reserved
FCR[7:6]: Receive FIFO Trigger Select
(logic 0 = default, RX trigger level =1)
These 2 bits are used to set the trigger level for the receive FIFO. The UART will issue a receive interrupt when
the number of the characters in the FIFO crosses the trigger level.
The Line Control Register is used to specify the asynchronous data communication format. The word or
character length, the number of stop bits, and the parity are selected by writing the appropriate bits in this
register.
LCR[1:0]: TX and RX Word Length Select
These two bits specify the word length to be transmitted or received.
LCR[2]: TX and RX Stop-bit Length Select
The length of stop bit is specified by this bit in conjunction with the programmed word length.
4.7
Logic 0 = No transmit FIFO reset (default).
Logic 1 = Reset the transmit FIFO pointers and FIFO level counter logic (the transmit shift register is not
cleared or altered). This bit will return to a logic 0 after resetting the FIFO.
Logic 0 = Normal Operation (default).
Logic 1 = DMA Mode.
Line Control Register (LCR) - Read/Write
T
B
ABLE
FCR
IT
0
0
1
1
BIT-1
BIT-2
-7
0
0
1
1
0
1
1
10: R
B
FCR
IT
0
1
0
1
-6
ECEIVE
LENGTH
BIT-0
T
5,6,7,8
W
6,7,8
RIGGER
0
1
0
1
1 (default)
ORD
5
R
FIFO T
ECEIVE
14
4
8
L
27
EVEL
RIGGER
Table-A. 16C550,
16C2550, 16C2552,
16C554, 16C580 com-
patible.
S
W
TOP BIT LENGTH
(B
5 (default)
ORD LENGTH
2.25V TO 5.5V DUART WITH 16-BYTE FIFO
L
C
1 (default)
EVEL
IT TIME
OMPATIBILITY
1-1/2
Table 10
6
7
8
2
S
(
S
ELECTION
))
shows the complete selections.
XR16L2552