xr16l2552im Exar Corporation, xr16l2552im Datasheet - Page 7

• Manufacturer Part Number: xr16l2552im
• Description: Industry Smallest Package Uart With 2.25v To 5.5v Operation
• Manufacturer: Exar Corporation

F
xr
REV. 1.1.1
The CPU interface is 8 data bits wide with 3 address lines and control signals to execute data bus read and
write transactions. The L2552 data interface supports the Intel compatible types of CPUs and it is compatible
to the industry standard 16C550 UART. No clock (oscillator nor external clock) is required to operate a data
bus transaction. Each bus cycle is asynchronous using CS#, IOR# and IOW# signals. Both UART channels
share the same data bus for host operations. The data bus interconnections are shown in
.
The L2552 can accept up to 5V inputs even when operating at 3.3V or 2.5V. But note that if the L2552 is
operating at 2.5V, its V
transceiver that is operating at 5V.
The RESET input resets the internal registers and the serial interface outputs in both channels to their default
state (see the
reset function in the device.
The L2552 provides a Device Identification code and a Device Revision code to distinguish the part from other
devices and revisions. To read the identification code from the part, it is required to set the baud rate generator
registers DLL and DLM both to 0x00. Now reading the content of the DLM will provide 0x02 to indicate L2552
and reading the content of DLL will provide the revision of the part; for example, a reading of 0x01 means
revision A.
2.0 FUNCTIONAL DESCRIPTIONS
2.1
2.2
2.3
2.4
IGURE
UART_CHSEL
UART_RESET
Pins in parentheses become available through the MF# pin. MF# A/B becomes RXRDY# A/B when AFR[2:1] = '10'. MF# A/B becomes OP2# A/B
when AFR[2:1] = '00'. MF# A/B becomes BAUDOUT# A/B when AFR[1:0] = '01'. RXRDY# pins available on 48-TQFP package.
UART_INTA
UART_INTB
UART_CS#
(RXRDYA#)
(RXRDYB#)
3.
TXRDYA#
TXRDYB#
CPU Interface
5-Volt Tolerant Inputs
Device Reset
Device Identification and Revision
IOW#
IOR#
XR16L2552 D
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
Table
13). An active high pulse of longer than 40 ns duration will be required to activate the
OH
ATA
may not be high enough to meet the requirements of the V
B
US
I
NTERCONNECTIONS
7
IOR#
IOW#
CHSEL
RESET
INTA
INTB
TXRDYA#
(RXRDYA#)
TXRDYB#
(RXRDYB#)
D0
D1
D2
D3
D4
D5
D6
D7
CS#
A0
A1
A2
2.25V TO 5.5V DUART WITH 16-BYTE FIFO
Channel A
Channel B
UART
UART
(BAUDOUTA#)
(BAUDOUTB#)
(OP2A#)
(OP2B#)
DTRA#
DSRA#
RTSA#
CTSA#
DTRB#
DSRB#
RTSB#
CTSB#
CDA#
CDB#
GND
RIA#
RIB#
VCC
TXA
RXA
RXB
TXB
VCC
IH
RS-232 Serial Interface
RS-232 Serial Interface
of a CPU or a serial
Figure
3.
XR16L2552