xr16l2552im Exar Corporation, xr16l2552im Datasheet - Page 9

• Manufacturer Part Number: xr16l2552im
• Description: Industry Smallest Package Uart With 2.25v To 5.5v Operation
• Manufacturer: Exar Corporation

xr
REV. 1.1.1
The INTA and INTB interrupt outputs change according to the operating mode and enahnced features setup.
Table 3
through
The L2552 includes an on-chip oscillator (XTAL1 and XTAL2) to produce a clock for both UART sections in the
device. The CPU data bus does not require this clock for bus operation. The crystal oscillator provides a
system clock to the Baud Rate Generators (BRG) section found in each of the UART. XTAL1 is the input to the
oscillator or external clock buffer input with XTAL2 pin being the output. For programming details, see
“Programmable Baud Rate Generator.”
2.9
2.10
RXRDY# A/B 0 = 1 byte.
TXRDY# A/B 0 = THR empty.
INTA/B Pin
INTA/B Pin
P
INS
INTA and INTB Ouputs
and
Crystal Oscillator or External Clock Input
Figure
Table 4
1 = no data.
1 = byte in THR.
0 = a byte in THR
1 = THR empty
0 = no data
1 = 1 byte
23.
(FIFO D
FCR
(FIFO D
(FIFO D
summarize the operating behavior for the transmitter and receiver. Also see
T
FCR B
FCR B
ABLE
BIT
ISABLED
T
-0=0
ABLE
T
2: TXRDY#
IT
ISABLED
IT
ISABLED
ABLE
-0 = 0
-0 = 0
)
3: INTA
4: INTA
0 = at least 1 byte in FIFO
1 = FIFO empty.
0 = FIFO empty.
1 = at least 1 byte in FIFO.
)
)
(DMA Mode Disabled)
AND
AND
AND
0 = at least 1 byte in FIFO
1 = FIFO empty
0 = FIFO below trigger level
1 = FIFO above trigger level
FCR Bit-3 = 0
INTB P
RXRDY# O
INTB P
INS
IN
9
O
UTPUTS IN
O
PERATION FOR
PERATION
FCR B
2.25V TO 5.5V DUART WITH 16-BYTE FIFO
IT
1 to 0 transition when FIFO reaches the trigger
level, or timeout occurs.
0 to 1 transition when FIFO empties.
0 = FIFO has at least 1 empty location.
1 = FIFO is full.
-0=1 (FIFO E
FIFO
F
(FIFO E
(FIFO E
OR
FCR B
FCR B
T
AND
RANSMITTER
R
ECEIVER
IT
IT
NABLED
NABLED
DMA M
-0 = 1
-0 = 1
(DMA Mode Enabled)
NABLED
FCR Bit-3 = 1
)
)
ODE
)
XR16L2552
Figure 18