xr16l2552im Exar Corporation, xr16l2552im Datasheet - Page 32

• Manufacturer Part Number: xr16l2552im
• Description: Industry Smallest Package Uart With 2.25v To 5.5v Operation
• Manufacturer: Exar Corporation

XR16L2552
2.25V TO 5.5V DUART WITH 16-BYTE FIFO
AFR[0]: Concurrent Write Mode
When this bit is set, the CPU can write concurrently to the same register in both UARTs. This function is
intended to reduce the dual UART initialization time. It can be used by the CPU when both channels are
initialized to the same state. The external CPU can set or clear this bit by accessing either register set. When
this bit is set, the channel select pin still selects the channel to be accessed during read operations. The user
should ensure that LCR Bit-7 of both channels are in the same state before executing a concurrent write to the
registers at address 0, 1, or 2.
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AFR[2:1]: MF# Output Select
These bits select a signal function for output on the MF# A/B pins. These signal function are described as:
OP2#, BAUDOUT#, or RXRDY#. Only one signal function can be selected at a time.
AFR[7:3]: Reserved
All are initialized to logic 0.
This register contains the device ID (0x02 for XR16L2552). Prior to reading this register, DLL and DLM should
be set to 0x00.
This register contains the device revision information. For example, 0x01 means revision A. Prior to reading
this register, DLL and DLM should be set to 0x00.
Enhanced features are enabled or disabled using this register. Bit 0-3 provide single or dual consecutive
character software flow control selection (see
are selected, the double 8-bit words are concatenated into two sequential characters. Caution: note that
whenever changing the TX or RX flow control bits, always reset all bits back to logic 0 (disable) before
programming a new setting.
4.14
4.15
4.16
Logic 0 = No concurrent write (default).
Logic 1 = Register set A and B are written concurrently with a single external CPU I/O write operation.
Device Identification Register (DVID) - Read Only
Device Revision Register (DREV) - Read Only
Enhanced Feature Register (EFR)
B
IT
0
0
1
1
-2
B
IT
0
1
0
1
-1
Table
12). When the Xon1 and Xon2 and Xoff1 and Xoff2 modes
32
MF# F
OP2# (default)
BAUDOUT#
Reserved
RXRDY#
UNCTION
xr
REV. 1.1.1