spear-09-h022 STMicroelectronics, spear-09-h022 Datasheet - Page 33

• Manufacturer Part Number: spear-09-h022
• Description: Spear Head Arm 926, 200k Customizable Easic Gates, Large Ip Portfolio Soc
• Manufacturer: STMicroelectronics

SPEAR-09-H022
9
9.1
Clock and reset system
Overview
The Clock System block is a fully programmable block able to generate all clocks necessary
at the chip, except for USB 2.0 Host and Device controllers, which have a dedicated PLL.
The clocks, at default operative frequency, are:
●
●
●
●
The frequencies are the maximum allowed value and the user can modify them by
programming dedicated registers.
The Clock System consists of 2 main parts: a Multi-Clock Generator block and an internal
PLL.
The Multi-Clock Generator block, starting from a reference signal (which generally is
delivered from the PLL), generates all clocks for the IPs of SPEAr Head200 according to
dedicated programmable registers.
The PLL, starting from the oscillator input of 12 MHz, generates a clock signal at a
frequency corresponding at the highest of the chip, which is the reference signal used by the
Multi-Clock Generator block to obtain all chip clocks. Its main features is the Electro-
Magnetic Interference reduction capability: user has the possibility to set up the PLL in order
to add a triangular wave to the VCO clock; the resulting signal will have the spectrum (and
the power) spread on a small range (programmable) of frequencies centred on F0 (VCO
Freq.), obtaining minimum electromagnetic emissions. This method replace all the other
traditional methods of E.M.I. reduction, as filtering, ferrite beads, chokes, adding power
layers and ground planets to PCBs, metal shielding etc., allowing sensible cost saving for
customers.
There are 3 operating modes:
clock @ 266 MHz for ARM system
clock @ 133 MHz for AHB Bus and AHB peripherals, eASIC MacroCell and Bus Bridge
included
clock @ 66.5 MHz for, APB Bus and APB peripherals, Bus Bridge included
clock @ 20 MHz for eASIC Programmable Interface
–
–
–
Normal mode: the Clock System delivers signals at the operative frequency. The
reference signal of the Multi-Clock Generator block is that generated by PLL
Pseudo-Functional mode: in this mode PLL is bypassed and the reference signal
is delivered from off-chip. The generated clocks are coherent with programmed
registers.
The purpose of Pseudo-Functional mode is let the rest of the chip properly work in
case of PLL failure.
This mode is set by assigning the following logic state to the Test pins:
TEST0
TEST1
TEST2
TEST3
Debug mode: is the operating state when the ARM is in Debug mode. The block
works as in Normal Mode but, APB peripheral clocks, eASIC clock and eASIC PI
clock are gated
→
→
→
→
1
0
0
0
Clock and reset system
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