spear-09-h022 STMicroelectronics, spear-09-h022 Datasheet - Page 49

• Manufacturer Part Number: spear-09-h022
• Description: Spear Head Arm 926, 200k Customizable Easic Gates, Large Ip Portfolio Soc
• Manufacturer: STMicroelectronics

SPEAR-09-H022
13.2.3
13.2.4
where xx is 16, the address of SMI in the memory map is from 0x1600_0000 to
0x19F_FFFF
Operation mode
Two operation modes exist:
In both cases SMI can work:
●
●
Hardware mode
At reset, the SMI operates in Hardware mode. In this mode, the transmit register and receive
register must not be accessed. They are managed by the SMI State Machine and used to
communicate with the external memory devices whenever an AHB master read or write to
an address in external memory.
Software mode
In Software Mode, transmit register and receive register are accessible. Direct AHB
transfers to/from external memories are not allowed.
Software mode is used to transfer any data or commands from the transmit register to
external memory and to read data directly in the receive register. The transfer is started
using a dedicated bit.
For example Software mode is used to erase Flash memory before writing. Erase cannot be
managed in Hardware mode due to incompatibilities which exist between Flash devices
from different vendors.
In Software mode, application code, being executed by the core, cannot be fetched from
external memory. It must either reside in internal memory, or be previously loaded from
external memory while the SMI is in Hardware mode.
Booting from external memory
SPEAr Head200 has an external boot from a Serial Flash at the Bank0 and the following
command sequence is sent to it:
●
●
●
●
All other banks are disabled at reset and must be enabled by setting dedicated bits before
they can be accessed.
–
–
or in Normal mode, up to a frequency of 20 MHz (19 Mhz at power on)
either in Fast mode, in a range frequency between 20 MHz and 50 MHz
Release from Deep Power-Down
29 µs delay
Read of Status register
Read of data bytes at memory start location
Hardware mode is used to serve AHB read and write requests. This is the
functional mode at reset.
Software mode is used to serve no AHB requests., during normal working
SPI memories
49/71