spear-09-h022 STMicroelectronics, spear-09-h022 Datasheet - Page 57

• Manufacturer Part Number: spear-09-h022
• Description: Spear Head Arm 926, 200k Customizable Easic Gates, Large Ip Portfolio Soc
• Manufacturer: STMicroelectronics

SPEAR-09-H022
Error Cases
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In all these cases, the SCL line is not held low; however, the SDA line can remain low due to
possible 0 bits transmitted last. It is then necessary to release both lines by software.
Figure 17. Transfer sequencing
Legend:
S=Start, P=Stop, A=Acknowledge, NA=Non-acknowledge
EVx=Event (with interrupt if ITE=1)
EV5: EVF=1, SB=1, cleared by reading SR1 register followed by writing DR register.
EV6: EVF=1, cleared by reading SR1 register followed by writing CR register (for example PE=1).
EV7: EVF=1, BTF=1, cleared by reading SR1 register followed by reading DR register.
EV8: EVF=1, BTF=1, cleared by reading SR1 register followed by writing DR register.
BERR: Detection of a Stop or a Start condition during a byte transfer. In this case, the
Event Flag and BERR bits are set by hardware with an interrupt.
AF: Detection of a non-acknowledge bit. In this case, the EVF and AF bits are set by
hardware with an interrupt. To resume, set the Start or Stop bit.
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C controller
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