spear-09-h022 STMicroelectronics, spear-09-h022 Datasheet - Page 65

• Manufacturer Part Number: spear-09-h022
• Description: Spear Head Arm 926, 200k Customizable Easic Gates, Large Ip Portfolio Soc
• Manufacturer: STMicroelectronics

SPEAR-09-H022
24.4
24.4.1
24.4.2
24.4.3
Power on sequence
Once the system is powered-on, the eASIC™ logic has to be properly configured before its
usage. In order to accomplish this task, two main operations have to be performed (both
using dedicated software routines running on the ARM9 microprocessor):
1.
2.
Both steeps are driven by the a control register programmable via APB bus.
Bitstream download
The bitstream download operation is responsible for the eASIC™ logic initialization, since
each configurable cell of the customizable logic is loaded with a data stream that represents
the mapped logic function. Each operation of this download is performed by a dedicated
software routine that read and writes data across the Control register reserved bits.
The bitstream is a 32 KByte data that is stored in the external non-volatile memory of the
SPEAr™ device.
Connection startup
Once the eASIC™ logic is up and running due to the Bitstream initialization, next steep is its
reset, in order to allow connections to the other IPs of the chip. The reset routine is activated
by programming the Control register.
Last steep is the enabling of needed connections, by setting the Status register.
Programming interface
In order to achieve the Bitstream download and the reset routine, a dedicate logic has been
embedded in the SPEAr Head200: the Programming Interface, which also includes the
Control register.
Bitstream download
Startup of connection between the eASIC™ MacroCell and the rest of the device
Customizable logic
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