a3p1000-1pqg208m Actel Corporation, a3p1000-1pqg208m Datasheet - Page 102

• Manufacturer Part Number: a3p1000-1pqg208m
• Description: Fpga Proasic 3 Family 1m Gates 130nm Cmos Technology 1.5v 208-pin Pqfp
• Manufacturer: Actel Corporation

Military ProASIC3/EL DC and Switching Characteristics
Table 2-154 • Input Data Register Propagation Delays
Table 2-155 • Input Data Register Propagation Delays
2- 88
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Note:
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Note:
ICLKQ
ISUD
IHD
ISUE
IHE
ICLR2Q
IPRE2Q
IREMCLR
IRECCLR
IREMPRE
IRECPRE
IWCLR
IWPRE
ICKMPWH
ICKMPWL
ICLKQ
ISUD
IHD
ISUE
IHE
ICLR2Q
IPRE2Q
IREMCLR
IRECCLR
IREMPRE
IRECPRE
IWCLR
IWPRE
ICKMPWH
ICKMPWL
For specific junction temperature and voltage supply levels, refer to
For specific junction temperature and voltage supply levels, refer to
Military-Case Conditions: T
Military-Case Conditions: T
Clock-to-Q of the Input Data Register
Data Setup Time for the Input Data Register
Data Hold Time for the Input Data Register
Enable Setup Time for the Input Data Register
Enable Hold Time for the Input Data Register
Asynchronous Clear-to-Q of the Input Data Register
Asynchronous Preset-to-Q of the Input Data Register
Asynchronous Clear Removal Time for the Input Data Register
Asynchronous Clear Recovery Time for the Input Data Register
Asynchronous Preset Removal Time for the Input Data Register
Asynchronous Preset Recovery Time for the Input Data Register
Asynchronous Clear Minimum Pulse Width for the Input Data Register
Asynchronous Preset Minimum Pulse Width for the Input Data Register
Clock Minimum Pulse Width HIGH for the Input Data Register
Clock Minimum Pulse Width LOW for the Input Data Register
Clock-to-Q of the Input Data Register
Data Setup Time for the Input Data Register
Data Hold Time for the Input Data Register
Enable Setup Time for the Input Data Register
Enable Hold Time for the Input Data Register
Asynchronous Clear-to-Q of the Input Data Register
Asynchronous Preset-to-Q of the Input Data Register
Asynchronous Clear Removal Time for the Input Data Register
Asynchronous Clear Recovery Time for the Input Data Register
Asynchronous Preset Removal Time for the Input Data Register
Asynchronous Preset Recovery Time for the Input Data Register
Asynchronous Clear Minimum Pulse Width for the Input Data Register
Asynchronous Preset Minimum Pulse Width for the Input Data Register
Clock Minimum Pulse Width HIGH for the Input Data Register
Clock Minimum Pulse Width LOW for the Input Data Register
Timing Characteristics
J
J
= 125°C, Worst-Case VCC = 1.14 V for A3PE600L and A3PE3000L
= 125°C, VCC = 1.425 V for A3PE600L and A3PE3000L
Description
Description
R e visio n 0
Table 2-5 on page 2-8
Table 2-5 on page 2-8
for derating values.
for derating values.
0.33 0.39
0.36 0.43
0.00 0.00
0.51 0.60
0.00 0.00
0.63 0.74
0.63 0.74
0.00 0.00
0.31 0.36
0.00 0.00
0.31 0.36
0.19 0.22
0.19 0.22
0.31 0.36
0.28 0.32
0.25 0.30
0.28 0.33
0.00 0.00
0.39 0.46
0.00 0.00
0.48 0.56
0.48 0.56
0.00 0.00
0.24 0.28
0.00 0.00
0.24 0.28
0.19 0.22
0.19 0.22
0.31 0.36
0.28 0.32
–1
–1
Std. Units
Std. Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns