a3p1000-1pqg208m Actel Corporation, a3p1000-1pqg208m Datasheet - Page 127

• Manufacturer Part Number: a3p1000-1pqg208m
• Description: Fpga Proasic 3 Family 1m Gates 130nm Cmos Technology 1.5v 208-pin Pqfp
• Manufacturer: Actel Corporation

Global Tree Timing Characteristics
Global clock delays include the central rib delay, the spine delay, and the row delay. Delays do not
include I/O input buffer clock delays, as these are I/O standard–dependent, and the clock may be driven
and conditioned internally by the CCC module. For more details on clock conditioning capabilities, refer
to the
present minimum and maximum global clock delays within each device. Minimum and maximum delays
are measured with minimum and maximum loading.
Timing Characteristics
Table 2-177 • A3PE600L Global Resource
Table 2-178 • A3PE3000L Global Resource
Parameter
t
t
t
t
t
F
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element,
3. For specific junction temperature and voltage supply levels, refer to
Parameter
t
t
t
t
t
F
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element,
3. For specific junction temperature and voltage supply levels, refer to
RCKL
RCKH
RCKMPWH
RCKMPWL
RCKSW
RCKL
RCKH
RCKMPWH
RCKMPWL
RCKSW
RMAX
RMAX
1.2 V DC Core Voltage
element, located in a lightly loaded row (single element is connected to the global net).
located in a fully loaded row (all available flip-flops are connected to the global net in the row).
values.
element, located in a lightly loaded row (single element is connected to the global net).
located in a fully loaded row (all available flip-flops are connected to the global net in the row).
values.
"Clock Conditioning Circuits" section on page
Military-Case Conditions: T
Military-Case Conditions: T
Input LOW Delay for Global Clock
Input HIGH Delay for Global Clock
Minimum Pulse Width HIGH for Global Clock
Minimum Pulse Width LOW for Global Clock
Maximum Skew for Global Clock
Maximum Frequency for Global Clock
Input LOW Delay for Global Clock
Input HIGH Delay for Global Clock
Minimum Pulse Width HIGH for Global Clock
Minimum Pulse Width LOW for Global Clock
Maximum Skew for Global Clock
Maximum Frequency for Global Clock
Description
Description
J
J
= 125°C, VCC = 1.14 V
= 125°C, VCC = 1.14 V
R e v i s i o n 0
2-116.
Table 2-177
Military ProASIC3/EL Low Power Flash FPGAs
Min.
Min.
1.80
1.79
Table 2-5 on page 2-8
Table 2-5 on page 2-8
1
1
–1
–1
to
Max.
Max.
2.06
2.09
0.30
Table 2-181 on page 2-115
2
2
Min.
Min.
2.12
2.11
Std.
1
Std.
1
Max.
Max.
2.42
2.45
0.35
for derating
for derating
2
2
Units
Units
MHz
MHz
2- 113
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns