a3p1000-1pqg208m Actel Corporation, a3p1000-1pqg208m Datasheet - Page 103

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a3p1000-1pqg208m

Manufacturer Part Number
a3p1000-1pqg208m
Description
Fpga Proasic 3 Family 1m Gates 130nm Cmos Technology 1.5v 208-pin Pqfp
Manufacturer
Actel Corporation
Datasheet
Table 2-156 • Input Data Register Propagation Delays
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Note:
ICLKQ
ISUD
IHD
ISUE
IHE
ICLR2Q
IPRE2Q
IREMCLR
IRECCLR
IREMPRE
IRECPRE
IWCLR
IWPRE
ICKMPWH
ICKMPWL
For specific junction temperature and voltage supply levels, refer to
Military-Case Conditions: T
Clock-to-Q of the Input Data Register
Data Setup Time for the Input Data Register
Data Hold Time for the Input Data Register
Enable Setup Time for the Input Data Register
Enable Hold Time for the Input Data Register
Asynchronous Clear-to-Q of the Input Data Register
Asynchronous Preset-to-Q of the Input Data Register
Asynchronous Clear Removal Time for the Input Data Register
Asynchronous Clear Recovery Time for the Input Data Register
Asynchronous Preset Removal Time for the Input Data Register
Asynchronous Preset Recovery Time for the Input Data Register
Asynchronous Clear Minimum Pulse Width for the Input Data Register
Asynchronous Preset Minimum Pulse Width for the Input Data Register
Clock Minimum Pulse Width HIGH for the Input Data Register
Clock Minimum Pulse Width LOW for the Input Data Register
J
= 125°C, Worst-Case VCC = 1.425 V for A3P1000
Description
R e v i s i o n 0
Table 2-6 on page 2-8
Military ProASIC3/EL Low Power Flash FPGAs
for derating values.
0.29 0.34
0.32 0.37
0.00 0.00
0.45 0.53
0.00 0.00
0.55 0.64
0.55 0.64
0.00 0.00
0.27 0.31
0.00 0.00
0.27 0.31
0.25 0.30
0.25 0.30
0.41 0.48
0.37 0.43
–1
Std. Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2- 89

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