a3p1000-1pqg208m Actel Corporation, a3p1000-1pqg208m Datasheet - Page 19

• Manufacturer Part Number: a3p1000-1pqg208m
• Description: Fpga Proasic 3 Family 1m Gates 130nm Cmos Technology 1.5v 208-pin Pqfp
• Manufacturer: Actel Corporation

Figure 2-2 • Devices Operating at 1.5 V Core – I/O State as a Function of VCCI and VCC Voltage Levels
Deactivation trip point:
V
V
Activation trip point:
a
d
= 0.85 V ± 0.25 V
= 0.75 V ± 0.25 V
VCC = 1.575 V
VCC = 1.425 V
PLL Behavior at Brownout Condition
Actel recommends using monotonic power supplies or voltage regulators to ensure proper power-up
behavior. Power ramp-up should be monotonic, at least until VCC and VCCPLX exceed brownout
activation levels. The VCC activation level is specified as 1.1 V worst-case (see
3 on page 2-6
When PLL power supply voltage and/or VCC levels drop below the VCC brownout levels (0.75 V
± 0.25 V), the PLL output lock signal goes low and/or the output clock is lost. Refer to the "Power-Up/-
Down Behavior of Low-Power Flash Devices" chapter of the
Guide
Internal Power-Up Activation Sequence
Output buffers, after 200 ns delay from input buffer activation.
VCC
1. Core
2. Input buffers
for information on clock and lock recovery.
Region 1: I/O Buffers are OFF
VCC = VCCI + VT
where VT can be from 0.58 V to 0.9 V (typically 0.75 V)
for more details).
Deactivation trip point:
Activation trip point:
V
V
a
d
= 0.9 V ± 0.3 V
= 0.8 V ± 0.3 V
Region 1: I/O buffers are OFF
Region 2: I/O buffers are ON.
I/Os are functional (except differential inputs)
but slower because VCCI / VCC are below
specification. For the same reason, input
buffers do not meet VIH / VIL levels, and
output buffers do not meet VOH / VOL levels.
buffers do not meet VOH / VOL levels.
meet VIH / VIL levels, and output
same reason, input buffers do not
is below specification. For the
but slower because VCCI
(except differential
I/Os are functional
R e v i s i o n 0
buffers are ON.
Region 4: I/O
Min VCCI datasheet specification
standard; i.e., 1.425 V or 1.7 V
voltage at a selected I/O
or 2.3 V or 3.0 V
Military ProASIC3/EL Low Power Flash FPGAs
Military ProASIC3/EL FPGA Fabric User’s
Region 3: I/O buffers are ON.
I/Os are functional; I/O DC
specifications are met,
but I/Os are slower because
the VCC is below specification.
Region 5: I/O buffers are ON
and power supplies are within
specification.
I/Os meet the entire datasheet
and timer specifications for
speed, VIH / VIL, VOH / VOL,
etc.
Figure 2-2
and
VCCI
Figure 2-
2 -5