a3p1000-1pqg208m Actel Corporation, a3p1000-1pqg208m Datasheet - Page 81

• Manufacturer Part Number: a3p1000-1pqg208m
• Description: Fpga Proasic 3 Family 1m Gates 130nm Cmos Technology 1.5v 208-pin Pqfp
• Manufacturer: Actel Corporation

Table 2-102 • Minimum and Maximum DC Input and Output Levels
Figure 2-14 • AC Loading
Table 2-103 • AC Waveforms, Measuring Points, and Capacitive Loads
Table 2-104 • 3.3 V GTL
Table 2-105 • 3.3 V GTL
3.3 V GTL
Drive
Strength
25 mA
Notes:
1. Currents are measured at 100°C junction temperature and maximum voltage.
2. Currents are measured at 125°C junction temperature.
3. Output drive strength is below JEDEC specification.
Input LOW (V)
VREF – 0.05
*
Speed
Grade
Std.
–1
Note:
Speed
Grade
Std.
–1
Note:
Measuring point = V
3
For specific junction temperature and voltage supply levels, refer to
For specific junction temperature and voltage supply levels, refer to
Military-Case Conditions: T
Worst-Case VCCI = 3.0 V, VREF = 0.8 V
Applicable to Pro I/Os for A3PE600L and A3PE3000L Only
Military-Case Conditions: T
Worst-Case VCCI = 3.0 V, VREF = 0.8 V
Applicable to Pro I/Os for A3PE600L and A3PE3000L Only
Voltage-Referenced I/O Characteristics
3.3 V GTL
Gunning Transceiver Logic is a high-speed bus standard (JESD8-3). It provides a differential amplifier input
buffer and an open-drain output buffer. The V
Timing Characteristics
Min.
–0.3
t
t
V
DOUT
0.80
0.68
DOUT
0.61
0.52
VREF – 0.05 VREF + 0.05
Input HIGH (V)
VIL
trip
VREF + 0.05
Max.
. See
2.05
1.75
2.05
1.75
t
t
DP
DP
V
Table 2-27 on page 2-27
0.05
0.05
0.04
0.03
t
t
DIN
DIN
Min.
V
J
J
2.33
1.98
2.33
1.98
Measuring
t
t
= 125°C, Worst-Case VCC = 1.14 V,
= 125°C, VCC = 1.425 V,
Point* (V)
PY
PY
VIH
Test Point
0.8
t
t
Max.
0.52
0.44
0.40
0.34
EOUT
EOUT
3.6
V
GTL
for a complete table of trip points.
CCI
R e v i s i o n 0
VREF (typ.) (V)
pin should be connected to 3.3 V.
Max.
V
VOL
2.02
1.72
2.02
1.72
t
t
0.4
V
TT
ZL
ZL
25
10 pF
0.8
2.05
1.75
2.05
1.75
VOH
t
t
Min.
ZH
ZH
V
–
Table 2-5 on page 2-8
Table 2-5 on page 2-8
Military ProASIC3/EL Low Power Flash FPGAs
mA mA
t
t
I
OL
25 25
LZ
LZ
VTT (typ.) (V)
I
OH
t
t
HZ
HZ
1.2
Max.
mA
I
268
OSL
4.23
3.60
4.23
3.60
t
t
ZLS
ZLS
1
for derating values.
for derating values.
Max.
I
mA
181
OSH
t
4.27
3.63
t
4.27
3.63
ZHS
ZHS
C
LOAD
1
10
µA
I
15
(pF)
IL
Units
Units
2
ns
ns
ns
ns
µA
2- 67
I
15
IH
2