a3p1000-1pqg208m Actel Corporation, a3p1000-1pqg208m Datasheet - Page 99
![no-image](/images/no-image-200.jpg)
a3p1000-1pqg208m
Manufacturer Part Number
a3p1000-1pqg208m
Description
Fpga Proasic 3 Family 1m Gates 130nm Cmos Technology 1.5v 208-pin Pqfp
Manufacturer
Actel Corporation
Datasheet
1.A3P1000-1PQG208M.pdf
(182 pages)
- Current page: 99 of 182
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Enable
Figure 2-28 • Timing Model of the Registered I/O Buffers with Synchronous Enable and Asynchronous Clear
Data
CLK
CLR
Fully Registered I/O Buffers with Synchronous Enable and
Asynchronous Clear
CC
BB
DD
Data Input I/O Register with
AA
Active High Enable
Active High Clear
Positive-Edge Triggered
D
E
DFN1E1C1
CLR
Q
EE
INBUF
Y
R e v i s i o n 0
Array
Core
INBUF
CLKBUF
Data_out
Military ProASIC3/EL Low Power Flash FPGAs
LL
HH
JJ
KK
GG
FF
Data Output Register and
Enable Output Register with
D
E
D
E
DFN1E1C1
DFN1E1C1
Active High Enable
Active High Clear
Positive-Edge Triggered
CLR
CLR
Q
Q
DOUT
EOUT
2- 85
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