hn58v256a Renesas Electronics Corporation., hn58v256a Datasheet - Page 18

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hn58v256a

Manufacturer Part Number
hn58v256a
Description
Memory>eeprom>parallel Eeprom
Manufacturer
Renesas Electronics Corporation.
Datasheet
HN58V256A Series, HN58V257A Series
2. Data Protection at V
Note: The EPROM should be kept in unprogrammable state during V
CE
OE
WE
V
V
Rev.5.00, Nov. 17.2003, page 18 of 22
: Don’t care.
CC
SS
: Pull-down to V
: Pull-up to V
When V
as a trigger and turn the EEPROM to program mode by mistake. To prevent this unintentional
programming, the EEPROM must be kept in an unprogrammable state while the CPU is in an unstable
state.
2.1 Protection by CE, OE, WE
2.2 Protection by RES (only the HN58V257A series)
To realize the unprogrammable state, the input level of control pins must be held as shown in the
table below.
The unprogrammable state can be realized by that the CPU’s reset signal inputs directly to the
EEPROM’s RES pin. RES should be kept V
The EEPROM breaks off programming operation when RES becomes low, programming
operation doesn’t finish correctly in case that RES falls low during programming operation. RES
should be kept high for 10 ms after the last data input.
CC
is turned on or off, noise on the control pins generated by external circuits (CPU, etc) may act
CC
9-
or
4-5
level.
V
SS
+-
CC
level.
CC
CPU
RESET
V
On/Off
CC
V
CC
*
Unprogrammable
1 µs min
Program inhibit
100 µs min
V
SS
SS
level during V
10 ms min
*
Unprogrammable
CC
CC
Program inhibit
on/off by using CPU RESET signal.
on/off.
V
CC

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