hn58v256a Renesas Electronics Corporation., hn58v256a Datasheet - Page 7

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hn58v256a

Manufacturer Part Number
hn58v256a
Description
Memory>eeprom>parallel Eeprom
Manufacturer
Renesas Electronics Corporation.
Datasheet
HN58V256A Series, HN58V257A Series
Write Cycle
Parameter
Address setup time
Address hold time
CE to write setup time (WE controlled)
CE hold time (WE controlled)
WE to write setup time (CE controlled)
WE hold time (CE controlled)
OE to write setup time
OE hold time
Data setup time
Data hold time
WE pulse width (WE controlled)
CE pulse width (CE controlled)
Data latch time
Byte load cycle
Byte load window
Write cycle time
Time to device busy
Write start time
Reset protect time*
Reset high time*
Notes: 1. t
Rev.5.00, Nov. 17.2003, page 7 of 22
2. This function is supported by only the HN58V257A series.
3. Use this device in longer cycle than this value.
4. t
5. Next read or write operation can be initiated after t
6. This parameter is sampled and not 100
7. A6 through A14 are page addresses and these addresses are latched at the first falling edge of
8. A6 through A14 are page addresses and these addresses are latched at the first falling edge of
9. See AC read characteristics.
no longer driven.
series) are used. This device automatically completes the internal write operation within this value.
HN58V257A series) are used.
WE.
CE.
DF
WC
and t
must be longer than this value unless polling techniques or RDY/Busy (only the HN58V257A
2, 6
DFR
2
are defined as the time at which the outputs achieve the open circuit conditions and are
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
AS
AH
CS
CH
WS
WH
OES
OEH
DS
DH
WP
CW
DL
BLC
BL
WC
DB
DW
RP
RES
tested.
Min*
0
50
0
0
0
0
0
0
70
0
200
200
100
0.3
100
120
0*
100
1
DW
5
if polling techniques or RDY/Busy (only the
3
Typ
Max
30
10*
4
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
ms
ns
ns
µs
µs
Test conditions

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