gs840fh32at-8i GSI Technology, gs840fh32at-8i Datasheet - Page 7

• Manufacturer Part Number: gs840fh32at-8i
• Description: 256k X 18, 128k X 32, 128k X 36 4mb Sync Burst Srams
• Manufacturer: GSI Technology

Mode Pin Functions
Note:
There is a pull-up device on the LBO pin and a pull down device on the ZZ pin, so those input pins can be unconnected and the chip will operate
in the default states as specified in the above tables.
Burst Counter Sequences
Note:
The burst counter wraps to initial state on the 5th clock.
Byte Write Truth Table
Notes:
1.
2.
3.
4.
Rev: 1.08 4/2007
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
1st address
2nd address
3rd address
4th address
Write all bytes
Write all bytes
All byte outputs are active in read cycles regardle
Byte Write Enable inputs B
All byte I/O’s remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.
Bytes “
Write byte
Write byte
Write byte
Write byte
Function
Read
Read
Power Down Control
Burst Order Control
Mode Name
C
” and “
C
D
A
B
D
” are only available on the x32 and x36 versions.
A[1:0] A[1:0] A[1:0] A[1:0]
00
01
10
11
GW
H
H
H
H
H
H
H
L
A
, B
01
10
00
11
B
, B
C
and/or B
Name
BW
10
11
00
01
LBO
H
Pin
L
L
L
L
L
L
X
ZZ
D
may be used in any combination with BW to write single or multiple bytes.
00
01
10
11
ss
H or NC
L or NC
State
of the state of Byte Write Enable inputs.
H
L
B
X
H
H
H
H
X
L
L
A
7/22
B
Standby, I
Note:
The burst counter wraps to initial state on the 5th clock.
Interleaved Burst
1st address
2nd address
3rd address
4th address
X
H
H
H
H
X
L
L
B
Linear Burst
Function
Active
DD
= I
B
X
H
H
H
H
X
L
L
SB
C
A[1:0] A[1:0] A[1:0] A[1:0]
GS840FH18/32/36AT-8/8.5/10/12
00
01
10
11
B
X
H
H
H
H
X
L
L
D
01
00
11
10
Notes
2, 3, 4
2, 3, 4
2, 3, 4
10
00
01
11
2, 3
2, 3
1
1
© 1999, GSI Technology
11
10
01
00