cp3cn17 National Semiconductor Corporation, cp3cn17 Datasheet - Page 136

• Manufacturer Part Number: cp3cn17
• Description: Reprogrammable Connectivity Processor With Can Interface
• Manufacturer: National Semiconductor Corporation

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the normal and the alternate modes with the SCIDL bit
equal to 0 and equal to 1.
Note that when data is shifted out on MDODI (master mode)
or MDIDO (slave mode) on the leading edge of the MSK
clock, bit 14 (16-bit mode) is shifted out on the second lead-
ing edge of the MSK clock. When data are shifted out on
MDODI (master mode) or MDIDO (slave mode) on the trail-
ing edge of MSK, bit 14 (16-bit mode) is shifted out on the
first trailing edge of MSK.
Data Out
Data Out
Data In
Data In
Data Out
MSK
MSK
Data In
MSK
Shift
Out
MSB
MSB
Shift
Out
Sample
Point
MSB
MSB
MSB
MSB
Sample
Point
Sample
Point
Shift
Out
MSB - 1
MSB - 1
Figure 65. Alternate Mode (SCIDL = 0)
Figure 63. Normal Mode (SCIDL = 0)
Figure 64. Normal Mode (SCIDL = 1)
MSB - 1
MSB - 1
MSB - 1
MSB - 1
MSB - 2
MSB - 2
MSB - 2
MSB - 2
MSB - 2
MSB - 2
136
19.2
In Master mode, the MSK pin is an output for the shift clock,
MSK. When data is written to the (MWDAT register), eight
or sixteen MSK clocks, depending on the mode selected,
are generated to shift the 8 or 16 bits of data and then MSK
goes idle again. The MSK idle state can be either high or
low, depending on the SCIDL bit.
MASTER MODE
Bit 1
Bit 1
Bit 1
Bit 1
Bit 1
Bit 1
(LSB)
(LSB)
Bit 0
Bit 0
End of Transfer
End of Transfer
(LSB)
(LSB)
(LSB)
(LSB)
Bit 0
Bit 0
Bit 0
Bit 0
End of Transfer
DS069
DS070
DS071