cp3cn17 National Semiconductor Corporation, cp3cn17 Datasheet - Page 153

• Manufacturer Part Number: cp3cn17
• Description: Reprogrammable Connectivity Processor With Can Interface
• Manufacturer: National Semiconductor Corporation

22.0 Multi-Function Timer
The Multi-Function Timer module contains a pair of 16-bit
timer/counters. Each timer/counter unit offers a choice of
clock sources for operation and can be configured to oper-
ate in any of the following modes:
22.1.1
The Timer/Counter block contains the following functional
blocks:
Processor-Independent Pulse Width Modulation (PWM)
mode, which generates pulses of a specified width and
duty cycle, and which also provides a general-purpose
timer/counter.
Dual-Input Capture mode, which measures the elapsed
time between occurrences of external events, and which
also provides a general-purpose timer/counter.
Dual Independent Timer mode, which generates system
timing signals or counts occurrences of external events.
Two 16-bit counters, Timer/Counter 1 (TCNT1) and Tim-
er/Counter 2 (TCNT2)
Two 16-bit reload/capture registers, TCRA and TCRB
Control logic necessary to configure the timer to operate
in any of the four operating modes
Interrupt control and I/O control logic
System
Timer/Counter Block
Reset
Clock
TB
Prescaler Register
Prescaler Counter
Synchr.
System
Clock
TPRSC
5-Bit
Clock Source
Figure 75. Multi-Function Timer Block Diagram
Figure 76. Multi-Function Timer Clock Source
External Event
No Clock
Prescaled Clock
Pulse Accumulator
External Event
Reload/Capture A
Reload/Capture B
Timer/Counter 1
Timer/Counter 2
Timer/Counter
PWM/Capture/Counter
Mode Select + Control
TCNT1
TCNT2
TCRA
TCRB
153
The timer unit uses two I/O pins, called TA and TB. The tim-
er I/O pins are alternate functions of the PI7 and PG4 port
pins, respectively. (The PG4/TB pin is only available on the
100-pin package.)
22.1
Figure 75 is a block diagram showing the internal structure
of the MFT. There are two main functional blocks: a Timer/
Counter and Action block and a Clock Source block. The
Timer/Counter and Action block contains two separate tim-
er/counter units, called Timer/Counter 1 and Timer/Counter
2.
In a power-saving mode that uses the low-frequency
(32.768 kHz) clock as the System Clock, the synchroniza-
tion circuit requires that the Slow Clock operate at no more
than one-fourth the speed of the 32.768 kHz System Clock.
22.1.2
The Clock Source block generates the signals used to clock
the two timer/counter registers. The internal structure of the
Clock Source block is shown in Figure 76.
Single-Input Capture and Single Timer mode, which pro-
vides one external event counter and one system timer.
Action
TIMER STRUCTURE
Clock Source Block
Interrupt A
Interrupt B
Counter 1
Counter 2
Select
Select
DS081
Clock
Clock
TA
TB
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Counter 1
Clock
Counter 2
Clock
DS082