cp3cn17 National Semiconductor Corporation, cp3cn17 Datasheet - Page 167
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cp3cn17
Manufacturer Part Number
cp3cn17
Description
Reprogrammable Connectivity Processor With Can Interface
Manufacturer
National Semiconductor Corporation
Datasheet
1.CP3CN17.pdf
(220 pages)
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23.2
The VTU contains a total of 19 user accessible registers, as
listed in Table 67. All registers are word-wide and are initial-
ized to a known value upon reset. All software accesses to
the VTU registers must be word accesses.
PERCAP1
PERCAP2
PERCAP3
PERCAP4
DTYCAP1
DTYCAP2
DTYCAP3
DTYCAP4
COUNT1
COUNT2
COUNT3
COUNT4
INTPND
CLK1PS
CLK2PS
IO1CTL
IO2CTL
INTCTL
MODE
Name
VTU REGISTERS
Table 67 VTU Registers
FF FF8Ah
FF FF8Ch
FF FF8Eh
FF FF9Ah
FF FF9Ch
FF FF9Eh
FF FF80h
FF FF82h
FF FF84h
FF FF86h
FF FF88h
FF FF98h
FF FF90h
FF FF92h
FF FF94h
FF FF96h
FF FFA0h
FF FFA2h
FF FFA4h
Address
Mode Control Register
I/O Control Register 1
I/O Control Register 2
Duty Cycle/Capture 1
Duty Cycle/Capture 2
Duty Cycle/Capture 3
Duty Cycle/Capture 4
Counter 1 Register
Counter 2 Register
Counter 3 Register
Counter 4 Register
Interrupt Pending
Period/Capture 1
Period/Capture 2
Period/Capture 3
Period/Capture 4
Interrupt Control
Clock Prescaler
Clock Prescaler
Description
Register 1
Register 2
Register
Register
Register
Register
Register
Register
Register
Register
Register
Register
167
23.2.1
The MODE register is a word-wide read/write register which
controls the mode selection of all four timer subsystems.
The register is clear after reset.
TxRUN
TMODx
TMOD2 T4RUN T3RUN TMOD1 T2RUN T1RUN
TMOD4 T8RUN T7RUN TMOD3 T6RUN T5RUN
15
7
14
6
Mode Control Register (MODE)
The Timer Run bit controls whether the corre-
sponding timer is stopped or running. If set,
the associated counter and clock prescaler is
started depending on the mode of operation.
Once set, the clock to the clock prescaler and
the counter are enabled and the counter will
increment each time the clock prescaler
counter value matches the value defined in
the associated clock prescaler field (CxPR-
SC).
0 – Timer stopped.
1 – Timer running.
The Timer System Operating Mode field en-
ables or disables the Timer Subsystem and
defines its operating mode.
00 – Low-Power Mode. All clocks to the
01 – Dual 8-bit PWM mode. Each 8-bit
10 – 16-bit PWM mode. The two 8-bit
11 – Capture Mode. Both 8-bit counters are
13
5
counter subsystem are stopped. The
counter is stopped regardless of the val-
ue of the TxRUN bits. Read operations
to the Timer Subsystem will return the
last value; software must not perform
any write operations to the Timer Sub-
system while it is disabled since those
will be ignored.
counter may individually be started or
stopped via its associated TxRUN bit.
The TIOx pins will function as PWM out-
puts.
counters are concatenated to form a sin-
gle 16-bit counter. The counter may be
started or stopped with the lower of the
two TxRUN bits, i.e. T1RUN, T3RUN,
T5RUN, and T7RUN. The TIOx pins will
function as PWM outputs.
concatenated and operate as a single
16-bit counter. The counter may be start-
ed or stopped with the lower of the two
TxRUN bits, i.e., T1RUN, T3RUN,
T5RUN, and T7RUN. The TIOx pins will
function as capture inputs.
12
4
11
3
10
2
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