cp3cn17 National Semiconductor Corporation, cp3cn17 Datasheet - Page 52
cp3cn17
Manufacturer Part Number
cp3cn17
Description
Reprogrammable Connectivity Processor With Can Interface
Manufacturer
National Semiconductor Corporation
Datasheet
1.CP3CN17.pdf
(220 pages)
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11.1
An external crystal network is connected to the X1CKI and
X1CKO pins to generate the Main Clock, unless an external
clock signal is driven on the X1CKI pin. A similar external
crystal network may be used at pins X2CKI and X2CKO for
the Slow Clock. If an external crystal network is not used for
the Slow Clock, the Slow Clock is generated by dividing the
fast Main Clock.
The crystal network you choose may require external com-
ponents different from the ones specified in this datasheet.
In this case, consult with National’s engineers for the com-
ponent specifications
The crystals and other oscillator components must be
placed close to the X1CKI/X1CKO and X2CKI/X2CKO de-
vice input pins to keep the printed trace lengths to an abso-
lute minimum.
Figure 4 shows the required crystal network at X1CKI/
X1CKO and optional crystal network at X2CKI/X2CKO.
Table 23 shows the component specifications for the main
Choose capacitor component values in the tables to obtain
the specified load capacitance for the crystal when com-
bined with the parasitic capacitance of the trace, socket, and
package (which can vary from 0 to 8 pF). As a guideline, the
load capacitance is:
C2 > C1
C1 can be trimmed to obtain the desired load capacitance.
The start-up time of the 32.768 kHz oscillator can vary from
one to six seconds. The long start-up time is due to the high
Crystal
Capacitor C1, C2
Crystal
Capacitor C1, C2
Component
Component
EXTERNAL CRYSTAL NETWORK
CL
=
C1
-------------------- -
C1
Table 23 Component Values of the High Frequency Crystal Circuit
Table 24 Component Values of the Low Frequency Crystal Circuit
×
+
C2
C2
Resonance Frequency
Type
Max. Serial Resistance
Max. Shunt Capacitance
Load Capacitance
Capacitance
Resonance Frequency
Type
Maximum Serial Resistance
Maximum Shunt Capacitance
Load Capacitance
Min. Q factor
Capacitance
+
Cparasitic
Parameters
Parameters
52
crystal network and Table 24 shows the component specifi-
cations for the 32.768 kHz crystal network.
Q value and high serial resistance of the crystal necessary
to minimize power consumption in Power Save mode.
11.2
The Main Clock is generated by the 12-MHz high-frequency
oscillator or driven by an external signal. It can be stopped
by the Power Management Module to reduce power con-
sumption during periods of reduced activity. When the Main
Clock is restarted, a 14-bit timer generates a Good Main
Clock signal after a start-up delay of 32,768 clock cycles.
This signal is an indicator that the high-frequency oscillator
is stable.
12 MHz/32.768 kHz
Crystal
MAIN CLOCK
Figure 4. External Crystal Network
12 MHz ± 20 ppm
C2
Values
C1
AT-Cut
N-Cut or XY-bar
22 pF
22 pF
50 Ω
7 pF
32.768 kHz
12.5 pF
Values
Parallel
40 kΩ
40000
25 pF
2 pF
X1CKI/X2CKI
X1CKO/X2CKO
GND
Tolerance
20%
Tolerance
N/A
20%
N/A
DS007
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