cp3cn17 National Semiconductor Corporation, cp3cn17 Datasheet - Page 4

• Manufacturer Part Number: cp3cn17
• Description: Reprogrammable Connectivity Processor With Can Interface
• Manufacturer: National Semiconductor Corporation

www.national.com
3.0
The CP3CN17 connectivity processor is a complete micro-
computer with all system timing, interrupt logic, program
memory, data memory, I/O ports included on-chip, making
them well-suited to a wide range of embedded applications.
The block diagram on page 1 shows the major on-chip com-
ponents of the CP3CN17.
3.1
The CP3CN17 implements the CR16C CPU core module.
The high performance of the CPU core results from the im-
plementation of a pipelined architecture with a two-bytes-
per-cycle pipelined system bus. As a result, the CPU can
support a peak execution rate of one instruction per clock
cycle.
For more information, please refer to the CR16C Program-
mer’s Reference Manual (document number 424521772-
101, which may be downloaded from National’s web site at
http://www.national.com).
3.2
The CP3CN17 supports a uniform linear address space of
up to 16 megabytes. Three types of on-chip memory occupy
specific regions within this address space:
The 256K bytes of Flash program memory are used to store
the application program and real-time operating system.
The Flash memory has security features to prevent uninten-
tional programming and to prevent unauthorized access to
the program code. This memory can be programmed with
an external programming unit or with the device installed in
the application system (in-system programming).
The 8K bytes of Flash data memory are used for non-vola-
tile storage of data entered by the end-user, such as config-
uration settings.
The 10K bytes of static RAM are used for temporary storage
of data and for the program stack and interrupt stack. Read
and write operations can be byte-wide or word-wide, de-
pending on the instruction executed by the CPU.
Up to 8M bytes of external memory can be added on an ex-
ternal bus. The external bus is only available on devices in
100-pin packages.
For Flash program and data memory, the device internally
generates the necessary voltages for programming. No ad-
ditional power supply is required.
3.3
The device has up to 40 software-configurable I/O pins, or-
ganized into five 8-pin ports called Port B, Port C, Port G,
Port H, and Port I. Each pin can be configured to operate as
a general-purpose input or general-purpose output. In addi-
tion, many I/O pins can be configured to operate as inputs
or outputs for on-chip peripheral modules such as the
UART, timers, or Microwire/SPI interface.
256K bytes of Flash program memory
8K bytes of Flash data memory
10K bytes of static RAM
Up to 8M bytes of external memory (100-pin devices)
Device Overview
CR16C CPU CORE
MEMORY
INPUT/OUTPUT PORTS
4
The I/O pin characteristics are fully programmable. Each pin
can be configured to operate as a TRI-STATE output, push-
pull output, weak pull-up input, or high-impedance input.
3.4
The Bus Interface Unit (BIU) controls access to internal/ex-
ternal memory and I/O. It determines the configured param-
eters for bus access (such as the number of wait states for
memory access) and issues the appropriate bus signals for
each requested access.
The BIU uses a set of control registers to determine how
many wait states and hold states are used when accessing
Flash program memory, and the I/O area (Port B and Port
C). At start-up, the configuration registers are set for slowest
possible memory access. To achieve fastest possible pro-
gram execution, appropriate values must be programmed.
These settings vary with the clock frequency and the type of
off-chip device being accessed.
3.5
The ICU receives interrupt requests from internal and exter-
nal sources and generates interrupts to the CPU. An inter-
rupt is an event that temporarily stops the normal flow of
program execution and causes a separate interrupt handler
to be executed. After the interrupt is serviced, CPU execu-
tion continues with the next instruction in the program fol-
lowing the point of interruption.
Interrupts from the timers, UART, Microwire/SPI interface,
and Multi-Input Wake-Up, are all maskable interrupts; they
can be enabled or disabled by software. There are 32 of
these maskable interrupts, assigned to 32 linear priority lev-
els.
The highest-priority interrupt is the Non-Maskable Interrupt
(NMI), which is generated by a signal received on the NMI
input pin.
3.6
The Multi-Input Wake-Up (MIWU) module can be used for
either of two purposes: to provide inputs for waking up (ex-
iting) from the Halt, Idle, or Power Save mode; or to provide
general-purpose edge-triggered maskable interrupts from
external sources. This 16-channel module generates four
programmable interrupts to the CPU based on the signals
received on its 16 input channels. Channels can be individ-
ually enabled or disabled, and programmed to respond to
positive or negative edges.
INTERRUPT CONTROL UNIT (ICU)
MULTI-INPUT WAKE-UP
BUS INTERFACE UNIT