msm7664 Oki Semiconductor, msm7664 Datasheet
msm7664
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msm7664 Summary of contents
Page 1
... MSM7664 NTSC/PAL Digital Video Decoder GENERAL DESCRIPTION The MSM7664 is an LSI device that decodes NTSC or PAL analog video signals into YCbCr and RGB digital data based on ITU-RBT.601. The device has built-in two channels of A/D converters and can accept composite video and S video signals for the input video signals. Composite video signals are converted to YCbCr and RGB digital data via the 2-dimensional Y/C separation circuit with an adaptive filter ...
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... Multiplex signal recognition (closed caption) During vertical blanking interval, data is output as 8-bit data C-bus interface 3.3 V single power supply (I tolerance) Package: 100-pin plastic TQFP (TQFP100-P-1414-0.50-K) (Product name: MSM7664TB) : NTSC/PAL ITU-RBT.601 : NTSC 4fsc : PAL Square Pixel 2 C-bus (only for ITU-RBT.601 mode). PEDL7664-01 ...
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... Semiconductor BLOCK DIAGRAM Decimation Decimation Filter Filter SW Matrix PEDL7664-01 MSM7664 3/76 ...
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... CLPOUT2 9 VRB2 10 AGND 11 AGND 12 VRB1 13 CLPOUT1 14 AMPOUT1 15 ADIN1 16 VRCL1 17 AGND VIN4 20 VIN3 21 VIN2 22 VIN1 23 VRT1 24 DAV 25 DD 100-Pin Plastic TQFP PEDL7664-01 MSM7664 75 HSYNC_L 74 VSYNC_L 73 VVALID 72 HVALID 71 ODD/EVEN 70 C[0] 69 C[1] 68 C[2] 67 C[3] 66 C[4] 65 C[5] 64 C[6] 63 C[7] 62 DGND Y[0] 59 Y[1] 58 Y[2] 57 Y[3] 56 Y[4] 55 Y[5] 54 Y[ ...
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... Composite-2 S-video 2 luminance signal (Y-2) input (leave open or connect to AGND when not used) Composite-1 S-video 1 luminance signal (Y-1) input (leave open or connect to AGND when not used) A/D converter reference voltage (high side) for composite/S-video (luminance signal) Digital power supply in A/D converter Digital ground in A/D converter PEDL7664-01 MSM7664 5/76 ...
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... When a double-speed input mode is used, input a double frequency to system clock. Data output B[7]: MSB, B[0]: LSB During RGB output mode: B 8-bit data output Other than RGB output mode: Hi-Z Output mode is set by pin 27 or 28, or register MRA [7:6]. Digital ground Digital power supply PEDL7664-01 MSM7664 6/76 ...
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... Digital power supply System clock input (selected by operation mode) Normal input mode NTSC ITU-RBT.601 13.5 MHz NTSC Square Pixel 12.272727 MHz NTSC 4fsc 14.31818 MHz PAL ITU-RBT.601 13.5 MHz PAL Square Pixel 14.75 MHz PEDL7664-01 MSM7664 Double-speed input mode 27 MHz 24.545454 MHz 28.63636 MHz 27 MHz 29.5 MHz 7/76 ...
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... Gain value setting: register ADC2[6:4] Input pin setting: register ADC1[2:0] Internal register setting is invalid when external pin mode is set. Selection of external field memory control signal output If field memory is not used, set M[ M[7:4] outputs are invalid 1: M[7:4] outputs are valid Digital ground Digital power supply PEDL7664-01 MSM7664 8/76 ...
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... VIN1 (pin 23) Composite-1 [001] VIN2 (pin 22) Composite-2 [010] VIN3 (pin 21) Composite-3 [011] VIN4 (pin 20) Composite-4 [100] VIN5 (pin 4) Composite-5 [101] VIN1 (pin 23) Y-1 VIN5 (pin 4) C-1 [110] VIN2 (pin 22) Y-2 VIN6 (pin 3) C-2 [111] Prohibited setting (ADC enters sleep state) Digital ground in A/D converter PEDL7664-01 MSM7664 9/76 ...
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... DD GND — — V — 2.2 IH1 0.8 ¥ (*1) — IH2 V — SYNC tip to white V 0.8 AIN peak level Ta — 0 PEDL7664-01 MSM7664 Rating Unit –0.3 to +4.5 V –0 –55 to +150 °C Typ. Max. Unit 3.3 3. — V — — V (*2) ...
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... ADV Symbol Condition Min. AD1 on I AD2 off 120 D1 CLKX2 = 27 MHz AD1 on I AD2 on 120 D2 CLKX2 = 27 MHz 1 DOFF I PEDL7664-01 MSM7664 , ADV , 3 Typ. Max. Unit — — 0 — +10 mA — 250 mA — +10 — ...
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... OD2X23 t CLKSEL : L 5 CXD21 t CLKSEL : L 4 CXD22 4.7 kW 200 C_SCL pull_up 4.7 kW 100 L_SCL pull_up t 200 RST_W PEDL7664-01 MSM7664 , 3.0 to 3.45 V, GND = Typ. Max. Unit 27.0 — MHz 28.63636 — MHz 24.545454 — MHz 29.5 — MHz — — 26 (24) ns — 22 (20) ns — ...
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... CLKSEL : H 3 OD2X13 t CLKSEL : H 6 CXD11 t CLKSEL : H 5 CXD12 4.7 kW 200 C_SCL pull_up 4.7 kW 100 L_SCL pull_up t 200 RST_W PEDL7664-01 MSM7664 , 3.0 to 3.45 V, GND = Typ. Max. Unit 13.5 — MHz 14.31818 — MHz 12.272727 — MHz 14.75 — MHz 60 % — — — ...
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... CXD22 t CXD21 t OD21 t OD2X21 t ODX21 t OD22 t OD2X22 t ODX22 t OD23 t OD2X23 t ODX23 Data delay Blank Active Data pixel rate absorption difference FIFO/FM Mode Amount of Delay FIFO 358T ± 358T FIFO 358T ± 358T FIFO-1 358T ±a FM 358T PEDL7664-01 MSM7664 14/76 ...
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... C-bus is indicated below ACK t C_SCL HD:STA HIGH SU:DAT SU:STA Parameter 2 C-bus can operate faster than at the PEDL7664-01 MSM7664 9 P 3-8 ACK Stop condition P t SU:STO Min. Max. Unit 0 100 kHz ms 4.7 ms 4.0 ms 4.7 ms 4.0 ms 4.7 300 ...
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... M[1] pin setting, 0: external mode, 1: internal register mode Input Pin VIN1 VIN2 VIN3 VIN4 Composite Composite Composite Composite Luminance Luminance OFF (Sleep) *: register default setting after LSI reset PEDL7664-01 MSM7664 2 C-bus or by ADC Selection VIN5 VIN6 ON OFF ON OFF ON OFF ON OFF ON OFF Composite ...
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... Semiconductor Manual Gain Control (analog AMP gain) Gain Setting Pins Register GAINS[2:0] ADC2[6:4] [000] [000] [001] [001] [010] [010] [011] [011] [100] [100] [101] [101] [110] [110] [111] [111] Set Gain Value Typ. Value (multiplication factor) 1.0 1.35 1.75 2.3 3.0 3.8 5.0 Undefined PEDL7664-01 MSM7664 17/76 ...
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... PAL signal) When a comb filter is not used, Y/C separation is performed by a trap filter. 2 C-bus. Default settings are indicated by 13.5 MHz* 12.272727 MHz 14.31818 MHz 13.5 MHz 14.75 MHz PEDL7664-01 MSM7664 18/76 ...
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... High range 4) Coring range selection (related register LUMC[3:2]) Off* 4LBS 5LBS 7LBS 5) Aperture weighting coefficient selection (related register LUMC[1:0]) 0* 0.25 0.75 1.50 Both coring and aperture compensation processes perform contour compensation. 6) Selection of pixel position compensating circuit usage (related register MRC[6]) Use* Do not use PEDL7664-01 MSM7664 19/76 ...
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... Color killer mode selection (related register MRB[5]) Auto color killer mode* Forced color killer 6) Parameter for fine adjustment of color subcarrier phase (related register HUE[7:0]) HUE control function 903 ms 225 ms 424 ms* 106 ms 0 PEDL7664-01 MSM7664 20/76 ...
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... FIFO-1 mode*: Sets and outputs a standard value for the number of pixels per 1H from the internal FIFO. This mode is also compatible (to a degree) with non-standard VTR signals. FIFO-2 mode: Sets and outputs a constant pixel number corresponding to the input H interval for the number of pixels per 1H from the internal FIFO. PEDL7664-01 MSM7664 21/76 ...
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... Multiplex signal detection HSYNC synchronization detection Internal FIFO overflow detection 6) Output signal phase control (related registers OPCY[1:0], OPCC[1:0]) Y and C phases can each be adjusted in the range of – pixels. PEDL7664-01 synchronization with HSYNC_L, VSYNC_L synchronization with HSYNC_L, VSYNC_L synchronization with HSYNC_L, VSYNC_L MSM7664 22/76 ...
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... The license to use the LSI chip for I Phillips Corporation by purchasing the LSI chip. 8. Test Control Block This block is used to test the LSI chip. Normally this block is not used standard of the Phillips Corporation systems is granted on the basis of the I PEDL7664-01 MSM7664 2 C patent of the 23/76 ...
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... Iuminance input black level sync 13 input sync-tip level NTSC/PAL; CVBS[7:0] input range PEDL7664-01 MSM7664 reserved +DC 24/76 ...
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... Cr6 Cr4 Cr2 Cr3 Cr2 Cr1 Cr0 C0 (LSB point point 0 YCbCr 4:1:1 format PEDL7664-01 MSM7664 ...
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... CVBS HVALID HSYNC_L VSYNC_L CSYNC_L VVALID ODD 262 263 264 265 266 267 268 269 270 271 CVBS HVALID HSYNC_L VSYNC_L CSYNC_L VVALID ODD Vertical Synchronizing Signal (60 Hz PEDL7664-01 MSM7664 283 284 285 26/76 ...
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... CVBS HVALID HSYNC_L CSYNC_L VSYNC_L VVALID ODD 309 310 311 312 313 314 315 316 317 318 CVBS HVALID HSYNC_L CSYNC_L VSYNC_L VVALID ODD Vertical Synchronizing Signal (50 Hz 336 337 338 PEDL7664-01 MSM7664 23 24 27/76 ...
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... EAV and SAV functionality. : clock periods 37 ns normal (1/27 MHz) : start of active video timing reference code : end of active video timing reference code Multiplexed video data Cb0 Y00 Cr0 Cb1 Y10 Cr1 Y11 4T Digital active line Video data block (1440T) PEDL7664-01 MSM7664 COLOR BURST Pedestal 28/76 ...
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... PEDL7664-01 MSM7664 during field 1 1: during field elsewhere 1: during field blanking SAV EAV P3, P2, P1, P0: Protection bit ...
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... CLKX2 changes to a single speed waveform, but the format after that is not changed. Cr n–4 Y n–3 Cb n–2 Y n–2 Cr n–2 Y n– Y(n–2) Cr0 Cb2 Cr2 Cb(n–2) Cr(n– R(n–2) G1 Cb2 Cr3 G(n–2) G(n– B(n–2) PEDL7664-01 MSM7664 Y(n–1) R(n–1) B(n–1) 30/76 ...
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... Y (7:0) C (7: hsync_l vsync_l hvalid vvalid odd-even y (7:0) c (7:0) RSTW WE HSYNC_L VSYNC_L HVLID VVALID ODD/EVEN RE RSTR Y (7:0) C (7:0) NTSC: ODD Field NTSC: EVEN Field PEDL7664-01 MSM7664 35 35 31/76 ...
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... Y (7:0) C (7: hsync_l vsync_l hvalid vvalid odd-even y (7:0) c (7:0) RSTW WE HSYNC_L VSYNC_L HVLID VVALID ODD/EVEN RE RSTR Y (7:0) C (7:0) PAL: ODD Field PAL: EVEN Field PEDL7664-01 MSM7664 39 38 32/76 ...
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... Square pixel 14.75 Front-porch Hsync back-porch 60 pixels Horizontal Timing Total Active Front- Pixels Pixels Porch 858 720 16 780 640 28 910 768 8 864 720 12 944 768 34 PEDL7664-01 MSM7664 Hsync Back- HBLK Porch Total 122 138 112 140 134 142 132 144 142 176 33/76 ...
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... Semiconductor Synchronizing Signal Timing (default timing when standard signal is input) HVALID VVALID HSYNC_L 16 pixels HVALID HSYNC_L VSYNC_L ODD (ODD) ODD (EVEN pixels 138 pixels 0 about 10.4 ms about 21.6 ms PEDL7664-01 MSM7664 1/13.5 MHz 34/76 ...
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... STATUS1 HVALID HSYNC_L Y[7:0] VBI Data Detection (when an S-Video signal is input): STATUS1 Timing VBI data detection results are output from the STATUS1 pin. Results of individual data detection are read from the register. Detection level 80 to 136 video in STATUS1 HVALID HSYNC_L Y[7:0] PEDL7664-01 MSM7664 35/76 ...
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... Slave Address (W) A Subaddress (1f) ≠ S Slave Address (W) A Subaddress (21) ≠ ...... Hereafter the above operations are repeated. ...... A Data Slave Address (R) A Data Reset Data Slave Address ( Data PEDL7664-01 MSM7664 Data Data 20 A' Data 21 A' 36/76 ...
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... The write attribute of a register does not match "X" (read ["1"]/write ["0"] control bit). The input timing is shown below. SDA ACK SCL S Slave Address Start Condition Description ACK 1 2 Subaddress PEDL7664-01 MSM7664 8 ACK Data P Stop Condition 37/76 ...
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... Notes 0 : ITU-RBT.656 01 : 8-bit (YCbCr 16-bit (Y + CbCr RGB 0 : NTSC 1 : PAL 0 : ITU-RBT.601 1 : Square Pixel 0 : twice the pixel frequency 1 : pixel frequency Normally set to a low level : low = 1000001, : high = 1000011 Normally set to a low level 0 : normal operation 1 : sleep PEDL7664-01 MSM7664 13.5 MHz (27.0 MHz) 13.5 MHz (27.0 MHz) 38/76 ...
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... AGCD16 AGCD15 AGCD14 AGCD13 AGCD12 AGCD11 AGCD10 1C AGCD27 AGCD26 AGCD25 AGCD24 AGCD23 AGCD22 AGCD21 AGCD20 1D WSSD7 WSSD6 WSSD5 WSSD4 WSSD3 WSSD2 WSSD1 WSSD0 1E MISC7 MISC6 MISC5 MISC4 MISC3 MISC2 MISC1 MISC0 1F AIREG7 AIREG6AIREG5AIREG4AIREG3AIREG2AIREG1AIREG0 PEDL7664-01 MSM7664 MRA3 MRA2 MRA1 MRA0 MRB3 MRB2 MRB1 MRB0 HSYT3 ...
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... CGMSE05 CGMSE04 2A CGMSE17 CGMSE16 CGMSE15 CGMSE14 2B CGMSE27 CGMSE26 CGMSE25 CGMSE24 2C WSS07 WSS06 WSS05 WSS04 2D WSS17 WSS16 WSS15 WSS14 PEDL7664-01 MSM7664 CCDE13 CCDE12 CCDE11 CCDE10 CGMSO03 CGMSO02 CGMSO01 CGMSO00 CGMSO23 CGMSO22 CGMSO21 CGMSO20 CGMSE03 CGMSE02 CGMSE01 CGMSE00 CGMSE13 CGMSE12 CGMSE11 ...
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... NTSC ITU-RBT.601 13.5 MHz 001: NTSC Square Pixel 010: NTSC 4fsc 100: PAL ITU-RBT.601 101: PAL Square Pixel 110, 111: Undefined Sampling rate is selected *0: External pin mode 1: Register mode PEDL7664-01 MSM7664 — — — 12.272727 MHz 14.31818 MHz 13.5 MHz 14.75 MHz ...
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... Non-adaptive comb filter (Operating mode is always fixed.) 10: Use trap filter. (Comb filter is not used.) 11: Undefined 2/3-line comb filter for NTSC Comb filter/trap filter for PAL 3-line comb filter for NTSC 2-line cosine comb filter for PAL PEDL7664-01 MSM7664 42/76 ...
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... During blanking, while VBI data is not detected * 255 235 Set to 0 Write only <address: $03> (*$0): –4 to +11 (–32 to +88 pixels (*$0): –4 to +11 (–32 to +88 pixels) PEDL7664-01 MSM7664 — 43/76 ...
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... The register control mode is a mode in which HSYNC is detected by the threshold level designated by STHR[6:0]. The MSM7664, which differs from its predecessor the MSM7662 in the sync detection technique, enhances the synchronous detection for signals including noise in the weak electrical field ...
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... Write only <address: $08> *0: OFF 1: ON *0: Do not use prefilter. 1: Use prefilter. *00: range0 (middle) 01: range1 10: range2 11: range3 (high) *00: coring off 01: 4LSB 10: 5LSB 11: 7LSB *00: 0.00 01: 0.25 10: 0.75 11: 1.50 PEDL7664-01 MSM7664 VVALT VVALT VVALT [2] [1] [ 45/76 ...
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... Write only <address: $0A> SSEPL SSEPL SSEPL SSEPL [6] [5] [4] [ *0: Do not use pedestal clamp. 1: Use pedestal clamp (AGC stops operating). $40 to $3F (*$00): –64 to +63 PEDL7664-01 MSM7664 [2] [1] [ SSEPL SSEPL SSEPL [2] [1] [ ...
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... Level difference 8 011: Level difference 12 100: Level difference 16 101: Level difference 20 110: Level difference 24 111: Always do averaging. *0: OFF OFF *1: ON 00: 0.500 color burst level *01: 0.250 color burst level 10: 0.125 color burst level 11: Color killer off PEDL7664-01 MSM7664 47/76 ...
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... Write only <address: $0D> $80 to $7F (*$00): –180 to +178.6 degrees Write only <address: $0E> Set to 0 *00: normal 01: forward l clock 10: backward 2 clock 11: backward l clock PEDL7664-01 MSM7664 [2] [1] [ 48/76 ...
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... HSYNC output signal is detected at sync threshold setting position. then output 1: VSYNC_L is output when a VSYNC input signal is detected. Set to 0 *0: Active 1: Hi-Z *0: NTSC/PAL identification 1: HLOCK sync detection *0: TV/VCR identification 1: CSYNC PEDL7664-01 MSM7664 49/76 ...
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... Write only <address: $12> manual *1: auto 000: 1.00 *001: 1.35 010: 1.75 011: 2.30 100: 3.00 101: 3.80 110: 5.00 111: Undefined 0: not initialize *1: initialize Set to 0 00: 2nd change end 01: 3rd change end *10: 3rd change loop 11: Undefined PEDL7664-01 MSM7664 — — — 50/76 ...
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... Undefined Write only <address: $14> ZLD[6] ZLD[5] ZLD[4] ZLD[ Set to 0 000: Undefined 001: 8 pixels *010: 16 pixels 011: 24 pixels 100: 32 pixels 101: 40 pixels 110: 48 pixels 111: 56 pixels PEDL7664-01 MSM7664 ZLD[2] ZLD[1] ZLD[ 51/76 ...
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... Set to 0 $4: – $3: +3 Write only <address: $16> Set to 0 *0: Single-sided feedback 1: Double-sided feedback *0: 30H free running mode 1: 6H free running mode $8: – $7: +7 PEDL7664-01 MSM7664 52/76 ...
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... NTSC (*21) NTSC only Write only <address: $1A> CGMS2 CGMS2 CGMS2 CGMS2 [6] [5] [4] [ Set to 0 $1f to $0f (*$0): –16 to +15 NTSC (*21) NTSC only PEDL7664-01 MSM7664 CGMS1 CGMS1 CGMS1 [2] [1] [ ...
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... NTSC (*21) PAL (*23) Write only <address: $1D> (*$0): – $1f to $0f (*$0): –16 to +15 PAL (*23) PAL only PEDL7664-01 MSM7664 AGCD1 AGCD1 AGCD1 [2] [1] [ AGCD2 AGCD2 AGCD2 [2] ...
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... Flag reset 1: Flag reset 1: Flag reset 1: Flag reset 1: Flag reset 1: Flag reset 1: Flag reset 1: Flag reset Start Reset flag (iiC; 0x1f) Read flag (iiC; 0x21) No Flag enable Yes Read data (iiC; 0x22 to 2d) PEDL7664-01 MSM7664 — — — 55/76 ...
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... NTSC, 1:PAL 0: FIFO1, 1:FIFO2 0: Non-detection, 1: Detection Read only <address: $21> VFLAG VFLAG VFLAG VFLAG [6] [5] [4] [3] — — — — — — — — PEDL7664-01 MSM7664 STATUS STATUS STATUS [2] [1] [0] — — — — — — VFLAG VFLAG VFLAG [2] [1] [0] — — — ...
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... Read only <address: $25> CCDE1 CCDE1 CCDE1 CCDE1 [6] [5] [4] [3] — — — — — — — — PEDL7664-01 MSM7664 CCDO0 CCDO0 CCDO0 [2] [1] [0] — — — — — — CCDO1 CCDO1 CCDO1 [2] [1] [0] — — — — ...
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... Read only <address: $28> CGMSO2 CGMSO2 CGMSO2 CGMSO2 [6] [5] [4] [3] — — — — — — — — PEDL7664-01 MSM7664 CGMSO0 CGMSO0 CGMSO0 [2] [1] [0] — — — — — — CGMSO1 CGMSO1 CGMSO1 [2] [1] [0] — — — — ...
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... Read only <address: $2B> CGMSE2 CGMSE2 CGMSE2 CGMSE2 [6] [5] [4] [3] — — — — — — — — PEDL7664-01 MSM7664 CGMSE0 CGMSE0 CGMSE0 [2] [1] [0] — — — — — — CGMSE1 CGMSE1 CGMSE1 [2] [1] [0] — — — — ...
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... Bits WSS data Read only <address: $2C> — — — — — — — — Read only <address: $2D> — — — — — — — — PEDL7664-01 MSM7664 — — — — — — — — — — — — 60/76 ...
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... All All All PEDL7664-01 MSM7664 Hi-Z PIN C[7:0], B[7:0] Y[7:0], C[7:0], B[7:0], M[7:3] *2 Undefined C[7:0], B[7:0] C[7:0], B[7:0] C[7:0], B[7:0] C[7:0], B[7:0] *2 C[7:0], B[7:0] Y[7:0], C[7:0], B[7:0], M[7:3] *2 Undefined C[7:0], B[7:0] C[7:0], B[7:0] C[7:0], B[7:0] C[7:0], B[7:0] *2 C[7:0], B[7:0] Y[7:0], C[7:0], B[7:0], M[7:3] *2 Undefined B[7:0] B[7:0] B[7:0] B[7:0] *2 None Y[7:0], C[7:0], B[7:0], M[7:3] *2 Undefined None None None None *2 ...
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... PEDL7664-01 MSM7664 +65 +81 +97 +113 +66 +82 +98 +114 +67 +83 +99 +115 +68 +84 +100 +116 +69 +85 +101 ...
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... –5 –4 –3 –2 – –5 –4 –3 –2 – PEDL7664-01 MSM7664 +10 +12 + +10 +12 + ...
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... E –50 –34 –18 –2 +14 F –49 –33 –17 –1 + +16 +32 +48 +17 +33 +49 +18 +34 +50 +19 +35 +51 +20 +36 +52 +21 +37 +53 +22 +38 +54 +23 +39 +55 +24 +40 +56 +25 +41 +57 +26 +42 +58 +27 +43 +59 +28 +44 +60 +29 +45 +61 +30 +46 +62 +31 +47 +63 PEDL7664-01 MSM7664 64/76 ...
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... Register Setting MSB [4] Value 1 0* (0x) 0* – – – – – – –10 +6 LSB LSB 7 7 – – – –6 + –5 + –4 + –3 + –2 + –1 +15 PEDL7664-01 MSM7664 65/76 ...
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... PEDL7664-01 MSM7664 +91.4 +113.9 +136.4 +158.9 +92.8 +115.3 +137.8 +160.3 +161.7 +94.2 +116.7 +139.2 +163.1 +95.6 +118.1 +140.6 +164.5 +97.0 +119.5 +142.0 +165.9 +98.4 +120.9 +143.4 +144.8 +167.3 +99.8 +122.3 +146.3 +168.8 +101.3 +123.8 +147 ...
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... PEDL7664-01 MSM7664 192 208 224 240 193 209 225 241 194 210 226 242 195 211 227 243 196 212 ...
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... Semiconductor Filter Characteristics Band Pass Filter (NTSC ITU-RBT.601) 0 –20 –40 –60 –80 –100 0 1 Band Pass Filter (PAL ITU-RBT.601) 0 –20 –40 –60 –80 –100 Frequency [MHz Frequency [MHz] PEDL7664-01 MSM7664 6 6 68/76 ...
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... Semiconductor 0 –20 –40 –60 –80 –100 –20 –40 –60 –80 –100 0 1 Trap Filter (NTSC ITU-RBT.601 Frequency [MHz] Trap Filter (PAL ITU-RBT.601 Frequency [MHz] PEDL7664-01 MSM7664 69/76 ...
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... Semiconductor 0 –20 –40 –60 –80 –100 –20 –40 –60 –80 –100 0 1 Prefilter Frequency [MHz] Sharp Filter Frequency [MHz] PEDL7664-01 MSM7664 6 6 70/76 ...
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... Semiconductor 0 –20 –40 –60 –80 –100 0 2 Decimation Filter Frequency [MHz] PEDL7664-01 MSM7664 12 71/76 ...
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... Power and GND lines for analog and A/D circuits must be wide and low impedance. 1000 pF 1000 pF 1000 pF 3 4.7 kW DAV MSM7664 DAGND DGND MODE[3:0] CLKX2 PEDL7664-01 MSM7664 Y(7:0) Video LSI C(7:0) B(7:0) HVALID VVALID ODD HSYNC_L VSYNC_L CLKX2O CLKXO OSC 72/76 ...
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... DAV MSM7664 HSYNC_L VSYNC_L DAGND DGND MODE[3:0] CLKX2 PEDL7664-01 MSM7664 Memory control signal M[7:4] Field mem- Y(7:0) ory Video LSI Field C(7:0) mem- ory B(7:0) CLKXO HVALID VVALID ODD CLKX2O OSC ...
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... Please contact us for these register settings. • Stable decode operations cannot always be guaranteed depending on input video signals. Each register can vary its setting values over a wide range but stable operations cannot be guaranteed for all setting values. PEDL7664-01 MSM7664 74/76 ...
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... Therefore, before you perform reflow mounting, contact Oki’s responsible sales person on the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). PEDL7664-01 MSM7664 (Unit : mm) Package material Epoxy resin Lead frame material ...
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... The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these part of the contents contained herein may be reprinted or reproduced without our prior permission. Copyright 1999 Oki Electric Industry Co., Ltd. Printed in Japan PEDL7664-01 MSM7664 76/76 ...