msm7664 Oki Semiconductor, msm7664 Datasheet - Page 43

• Manufacturer Part Number: msm7664
• Description: Ntsc/pal Digital Video Decoder
• Manufacturer: Oki Semiconductor

¡ Semiconductor
Mode Register C (MRC)
Note:
Horizontal Sync Trimmer (HSYT)
Note:
Default
Recommended Value
Default
Recommended Value
MRC[7]
MRC[6]
MRC[5]
MRC[4]
Note: This register is valid when a 2x clock (27 MHz) is input.
MRC[3]
MRC[2]
MRC[1:0]
HSYT[7:4]
HSYT[3:0]
Register Name
Register Name
This register decides automatically when the sampling frequency of input signals is
ITU-RBT.601.
The HSYT signal provides the clamp timing to the A/D converter during digital clamp
or hybrid clamp mode. Because this signal can move to the pedestal position, the
pedestal clamp can be used. However, this signal can not be observed from outside.
NTSC/PAL auto select
Pixel alignment
Pixel sampling rate
Data-pass control
SAV, EAV V-status
RGB output level
Undefined
HSY start trimmer (¥ 8 pixels)
HSY stop trimmer (¥ 8 pixels)
HSYT[7] HSYT[6] HSYT[5] HSYT[4] HSYT[3] HSYT[2] HSYT[1] HSYT[0]
MRC[7] MRC[6] MRC[5] MRC[4] MRC[3] MRC[2] MRC[1] MRC[0]
1
1
0
0
0
0
0
0
Write only
Write only
—
0
0
0
*1: Auto
*0: Use pixel position compensating circuit.
*0: (4:2:2)
*0: Use DECIMATOR at 2x sampling.
*0: During blanking, V = 1
*0: 0 to 255
0: Fix
1: Do not use pixel position compensating circuit.
1: (4:1:1)
1: Do not use DECIMATOR.
1: During blanking, while VBI data is not
1: 16 to 235
detected, V = 1
Set to 0
$C to $B (*$0): –4 to +11 (–32 to +88 pixels)
$C to $B (*$0): –4 to +11 (–32 to +88 pixels)
0
0
0
0
<address: $02>
<address: $03>
—
0
0
0
—
0
0
0
PEDL7664-01
0
0
0
0
MSM7664
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0
0
0
0