msm7664 Oki Semiconductor, msm7664 Datasheet - Page 22

• Manufacturer Part Number: msm7664
• Description: Ntsc/pal Digital Video Decoder
• Manufacturer: Oki Semiconductor

¡ Semiconductor
7) Field memory control signals
5. Epilogue Block
The Epilogue Block outputs the UV signal from the Chrominance block and the Y signal from the
Luminance block in a format based on a signal obtained from the control register setting.
This block can select the following modes.
1) Output mode selection (related register MRA[7:6])
2) Enable Blue Back display when synchronization fails (related register MRB[4])
3) Selection of YCbCr signal output format (related register MRC[5])
4) Output pin enable selection (related registers OMR[2], MISC[1:0])
5) Various mode detection (related register OMR[1:0])
6) Output signal phase control (related registers OPCY[1:0], OPCC[1:0])
If the FM-2 mode uses external field memory (2 Mb ¥ 2) instead of the internal FIFO, field
memory control signals are supplied from pins M[7:4]. At this time, pin M[0] requires to be
set to "H".
1-1) ITU-RBT.656 (SAV, EAV, blank processing)
1-2) * 8-bit (YCbCr) output (2x pixel clock)
1-3) 16-bit (8-bit Y/8-bit CbCr) (pixel clock)
1-4) 24-bit RGB (8 bits each)
The chrominance signal (U, V component) outputs Cb and Cr data to the C pin in an output
format to be described later.
Pins that become high impedance are determined by setting. See "Output Pin Control Table"
described later.
Y and C phases can each be adjusted in the range of –2 to +1 pixels.
FM-1 mode:
FM-2 mode:
OFF
ON*
YCbCr
YCbCr
High-impedance
Output enable*
NTSC/PAL detection
Multiplex signal detection
HSYNC synchronization detection
Internal FIFO overflow detection
This mode outputs the decoded results according to the SYNC signal.
Usage of external field memory is required to manage the number of pixels
and to absorb jitter.
Memory control signals are to be generated externally.
This mode is compatible with considerably distorted non-standard VTR
signals. Jitter is absorbed by using external field memory (2 Mb ¥ 2) and the
standard value is set as the pixel number.
Field memory control signals are output simultaneously from M[7:4].
4 : 2 : 2*
4 : 1 : 1
synchronization with HSYNC_L, VSYNC_L
synchronization with HSYNC_L, VSYNC_L
synchronization with HSYNC_L, VSYNC_L
PEDL7664-01
MSM7664
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