msm7664 Oki Semiconductor, msm7664 Datasheet - Page 21

• Manufacturer Part Number: msm7664
• Description: Ntsc/pal Digital Video Decoder
• Manufacturer: Oki Semiconductor

¡ Semiconductor
7) Vertical color filter (related register CHRC[6:4])
In this block, chroma signals pass through a bandpass filter to cut out unnecessary band.
To maintain a constant chroma level, these signals then pass through an ACC compensating
circuit and are UV demodulated. (The filter can be bypassed.)
If the demodulated result does not reach a constant level, color killer signals are generated to fix
the ACC gain. This functions as an auto color killer control circuit.
The UV demodulated results pass through a low-pass filter and are output as chrominance
signals.
4. Synchronization Block
This block processes the sync signals. Synchronous signals are generated for chip output and for
internal use. Various signals are output from this block and the following operating modes can
be selected.
1) Adjustment of SYNC threshold level (internal sync) (related register STHR[7:0])
2) Fine adjustment of HSY (Horizontal Sync Clamp) signal (related registers HSYT[7:4], HSYT[3:0],
3) Fine adjustment of HSYNC_L signal (related register HSDL[7:0])
4) HVALID control (related registers HVALT[7:4], HVALT[3:0])
5) VVALID control (related registers VVALT[7:4], VVALT[3:0])
6) FIFO and Field Memory mode selection (related register MRB[7:6])
Averaging computation is made for the lines before and after the U, V demodulated signal.
This is likely to make the image appear smooth.
Using a register, it is possible to select the modes of either to carry out or not carry out the
averaging operation based on the correlation between the previous and next lines, or not to
carry out the averaging operation at all. In addition, it is also possible to change the level of
judging the correlation using a register setting.
SYNC detection level is set.
MRB[3:2])
2-1) Fine adjustment of HSY signal (start side)
2-2) Fine adjustment of HSY signal (stop side)
The HSY signal provides the sync-tip and clamp timing to the A/D converter.
This signal is used for digital clamp, but can not be observed from outside.
HSYNC_L signal output position is adjusted.
4-1) Fine adjustment of HVALID signal (start side)
4-2) Fine adjustment of HVALID signal (stop side)
Data signals are transferred at the rising edge of the HVALID signal.
5-1) Fine adjustment of VVALID signal (start side)
5-2) Fine adjustment of VVALID signal (stop side)
FIFO-1 mode*: Sets and outputs a standard value for the number of pixels per 1H from the
FIFO-2 mode: Sets and outputs a constant pixel number corresponding to the input H
internal FIFO.
This mode is also compatible (to a degree) with non-standard VTR signals.
interval for the number of pixels per 1H from the internal FIFO.
PEDL7664-01
MSM7664
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