msm7664 Oki Semiconductor, msm7664 Datasheet - Page 49

• Manufacturer Part Number: msm7664
• Description: Ntsc/pal Digital Video Decoder
• Manufacturer: Oki Semiconductor

¡ Semiconductor
Output phase control for data C (OPCC)
Note:
Note:
Optional Mode Register (OMR)
Note:
Note:
Note:
Note:
Default
Recommended Value
Default
Recommended Value
OPCC[7]
OPCC[6]
OPCC[5:2]
OPCC[1:0]
OMR[7]
OMR[6]
OMR[5:3]
OMR[2]
OMR[1]
OMR[0]
Register Name
Register Name
The stability is increased when this setting is made ON at the time of decoding signals
under weak electric fields.
The output phase of data C is controlled.
When the HSYNC output signal is detected at sync threshold setting position, it is
hardly affected by noise.
When a non-standard signal is decoded, the output is stabilized after the VSYNC_L
input signal is detected (setting 1).
This register selects either normal or Hi-Z as the output pin status in SLEEP mode.
OMR[1:0] correspond to the STATUS[2:3] output of output pins.
Undefined
Anti-noise circuit
Undefined
Output phase control for data C
HSYNC output timing select *0: HSYNC output signal is detected near sync
VSYNC output timing select *0: VSYNC_L is synchronized to HSYNC_L and
Undefined
Hi-Z output in SLEEP mode
Status2 output mode
Status3 output mode
OPCC[7] OPCC[6] OPCC[5] OPCC[4] OPCC[3] OPCC[2] OPCC[1] OPCC[0]
OMR[7] OMR[6] OMR[5] OMR[4] OMR[3] OMR[2] OMR[1] OMR[0]
0
0
0
1
0
0
0
1
Write only
Write only
*00: normal
01: forward l clock
10: backward 2 clock
11: backward l clock
0
0
0
0
*0: OFF
*0: Active
*0: NTSC/PAL identification
*0: TV/VCR identification
1: ON
1: HSYNC output signal is detected at sync
1: VSYNC_L is output when a VSYNC input
1: Hi-Z
1: HLOCK sync detection
1: CSYNC
Set to 0
Set to 0
threshold and sync tip.
threshold setting position.
then output
signal is detected.
Set to 0
0
0
0
0
<address: $0F>
<address: $10>
0
0
0
0
0
0
0
0
PEDL7664-01
0
0
0
0
MSM7664
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0
0
0
0