tea5766uk NXP Semiconductors, tea5766uk Datasheet - Page 18

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tea5766uk

Manufacturer Part Number
tea5766uk
Description
Tea5766uk Stereo Fm Radio + Rds
Manufacturer
NXP Semiconductors
Datasheet

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Fig 7. SPI-bus interrupt sequence, read and write operation
(1) Interrupt events that occur outside of the region A-B set their respective flag bits in the normal way immediately and can thus trigger a hardware interrupt if the mask
(2) Effectively interrupts are enabled at the first falling edge of SCL after CS has gone HIGH.
(3) Interrupt events that occur between A and B set their respective flags after the mask bits are cleared, if the cause for the interrupt is still present at point B.
(4) All interrupt mask bits are cleared after the interrupt flag and mask bytes are read.
(5) Software writes to the mask register and enables the required mask bits. Any flags currently set will then trigger a hardware interrupt.
(6) INTX is set HIGH (inactive) after the interrupt flag and mask register are read.
bits are set.
MOSI
CS
interrupt event
interrupt flag bit
interrupt mask bit
INTX
subaddress
R/
W
(1)
A
INTFLAG
data
INTMSK
data
B
(2)
(3)
(4)
(6)
subaddress
R/
W
INTFLAG
data
INTMSK
data
(5)
(5)
001aaf445

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