tea5766uk NXP Semiconductors, tea5766uk Datasheet - Page 36

• Manufacturer Part Number: tea5766uk
• Description: Tea5766uk Stereo Fm Radio + Rds
• Manufacturer: NXP Semiconductors

NXP Semiconductors
TEA5766UK_1
Product data sheet
Fig 18. SPI transfer, 3 wire-mode
Fig 19. SPI-bus timing diagram
OUTPUT)
(SPICLK)
BUSEN
CLOCK
INPUT)
(MISO
(MOSI
DATA
DATA
(CS)
BUSEN
CLOCK
DATA
t
t
t
t
T
t
t
t
t
t
t
t
t
SPIR
SPIF
SPILEAD
SPIA
SPICLKH
SPICLKL
SPILAG
SPIOH
SPIDIS
SPIDSU
SPIDH
SPIDV
CLCL
= SPI fall time: 5 ns < t
= SPI rise time: 5 ns < t
= SPI access time (slave): > 150 ns.
= SPI enable to output data valid time: < 240 ns.
= clock cycle time: > 400 ns.
= SPI data hold time (master or slave): > 5 ns.
= SPI output data hold time: > 0 s.
= SPI disable time (slave): 0 ns < t
= SPI enable lag time: > 250 ns.
t
= SPI data set-up time (master or slave): > 5 ns.
SPIA
= SPICLK LOW time: > 190 ns.
= SPI enable lead time: > 250 ns.
= SPICLK HIGH time: > 190 ns.
t
-
SPIF
t
SPILEAD
t
SPIDSU
SLAVE MSB/LSB OUT
-
MSB/LSB IN
A4
SPIF
t
t
SPICLKH
SPIDH
SPIR
A3
t
SPIF
< 50 ns.
< 50 ns.
T
A2
CLCL
SPIDIS
t
SPICLKL
A1
Rev. 01 — 22 March 2007
< 167 ns.
A0
R/W
t
SPIR
t
SPIOH
t
SPIDV
D15
D14
t
SPIDSU
SLAVE LSB/MSB OUT
LSB/MSB IN
D13
D12
t
SPIDH
t
SPIDH
D11 to D1
TEA5766UK
Stereo FM radio + RDS
NOT DEFINED
© NXP B.V. 2007. All rights reserved.
t
SPILAG
D0
t
t
SPIR
SPIDIS
001aaf451
001aaf452
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