hi-3585 Holt Integrated Circuits, Inc., hi-3585 Datasheet - Page 4

• Manufacturer Part Number: hi-3585
• Description: Terminal Ic With Spi Interface
• Manufacturer: Holt Integrated Circuits, Inc.

FUNCTIONAL DESCRIPTION
CONTROL WORD REGISTER
The HI-3585 contains a 16-bit Control Register which is used to
configure the device. Control Register bits CR15 - CR0 are loaded
from a 16-bit data value appended to SPI instruction 10 hex. The
Control Register contents may be read using SPI instruction 0B
hex. Each bit of the Control Register has the following function:
(MSB)
(LSB)
CR10
CR11
CR12
CR13
CR14
CR15
CR1
CR2
CR3
CR4
CR5
CR6
CR7
CR8
CR9
CR
Bit
Cr0
FUNCTION STATE
Source Select
Transmission
ARINC Clock
Enable Label
ARINC Label
Enable Mode
Parity Check
Recognition
Transmitter
Transmitter
Transmitter
Line Driver
Data Rate
Data Rate
Definition
Definition
Receiver
Parity Bit
Receiver
Receiver
Bit Order
Self Test
Decoder
Disable
RFLAG
TFLAG
Enable
Enable
Select
Select
Parity
-
-
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
-
-
ARINC bits 10 and 9 must match CR7 and CR8
Line Driver disabled (force outputs to Null state)
TFLAG goes high when transmit FIFO is empty
RFLAG goes high when receive FIFO is empty
Data rate = CLK/10
Data rate = CLK/80
The transmitter’s digital outputs are internally
TFLAG goes high when transmit FIFO is full
RFLAG goes high when receive FIFO is full
ARINC CLK = ACLK divided by the value
programmed with SPI Instruction 07 hex
Data rate = CLK/10, O/P slope = 1.5us
Data rate = CLK/80, O/P slope = 10us
Label bit order reversed (See Table 2)
connected to the receiver logic inputs
ARINC CLK = ACLK input frequency
Label bit order same as transmitted /
the ARINC bit 10 must match this bit
Transmit whenever data is available
the ARINC bit 9 must match this bit
Receiver odd parity check enabled
Transmitter 32nd bit is Even parity
Transmitter 32nd bit is Odd parity
Receiver parity check disabled
If receiver decoder is enabled,
If receiver decoder is enabled,
Transmitter 32nd bit is parity
Transmitter 32nd bit is data
Receiver decoder disabled
Label recognition disabled
Label recognition enabled
Start transmission by SPI
received (See Table 2)
in the Transmit FIFO
Line Driver enabled
DESCRIPTION
Normal operation
instruction12 hex
(ARINC 429 High-Speed)
(ARINC 429 Low-Speed)
HOLT INTEGRATED CIRCUITS
HI-3585
4
STATUS REGISTER
The HI-3585 contains an 8-bit Status Register which can be
interrogated to determine the status of the ARINC receiver, data
FIFOs and transmitter. The contents of the Status Register are
output using SPI instruction 0A hex. Unused bits are output as
Zeros. The following table defines the Status Register bits.
(MSB)
(LSB)
SR0
SR1
SR2
SR3
SR4
SR5
SR6
SR7
SR
Bit
Transmit FIFO
Transmit FIFO
Transmit FIFO
FUNCTION
Receive FIFO
Receive FIFO
Receive FIFO
Not used
Not used
Half Full
Half Full
Empty
Empty
Full
Full
STATE
0
1
0
1
0
1
0
1
0
1
0
1
0
0
Receiver FIFO contains valid data
Sets to One when all data has
been read. RFLAG pin reflects the
state of this bit when CR15=0
Receiver FIFO is empty
Receiver FIFO holds less than 16
words
Receiver FIFO holds at least 16
words
Receiver FIFO not full. RFLAG pin
reflects the state of this bit when
CR15=1
Receiver FIFO full. To avoid data
loss, the FIFO must be read within
one ARINC word period
Transmit FIFO not empty.
Sets to One when all data has
been sent. TFLAG pin reflects the
state of this bit when CR14=0
Transmit FIFO is empty.
Transmit FIFO contains less than 16
words
Transmit FIFO contains at least 16
words
Transmit FIFO not full. TFLAG pin
reflects the state of this bit when
CR14=1
Transmit FIFO full.
Always “0”
Always “0”
DESCRIPTION