hi-3585 Holt Integrated Circuits, Inc., hi-3585 Datasheet - Page 5

• Manufacturer Part Number: hi-3585
• Description: Terminal Ic With Spi Interface
• Manufacturer: Holt Integrated Circuits, Inc.

FUNCTIONAL DESCRIPTION (cont.)
ARINC 429 RECEIVER
ARINC BUS INTERFACE
Figure 1 shows the input circuit for the on-chip ARINC 429 line
receiver.
detection levels:
The HI-3585 guarantees recognition of these levels with a common
mode voltage with respect to GND less than ±30V for the worst case
condition (3.15V supply and 13V signal level).
Design tolerances guarantee detection of the above levels, so the
actual acceptance ranges are slightly larger. If the ARINC signal
(including nulls) is outside the differential voltage ranges, the HI-
3585 receiver rejects the data.
ARINC 429 DATA FORMAT
Control Register bit CR11 controls how individual bits in the
received or transmitted ARINC word are mapped to the HI-3585
SPI data word bits during data read or write operations.
following table describes this mapping:
ARINC bit 8
ARINCbit
CR11=0
CR11=1
RINA-40
RINB-40
SPI
bit
RINA
RINB
1
1
STATE
ZERO
The ARINC 429 specification requires the following
NULL
ONE
2
7
2
3
6
3
Table 2. SPI / ARINC bit-mapping
FIGURE 1. ARINC RECEIVER INPUT
GND
GND
VDD
VDD
4
5
4
5
4
5
DIFFERENTIAL VOLTAGE
+6.5 Volts to +13 Volts
+2.5 Volts to -2.5 Volts
6
3
6
-6.5 Volts to -13 Volts
7
2
7
8
1
8
DIFFERENTIAL
AMPLIFIERS
9
9
9
10
10
10
HOLT INTEGRATED CIRCUITS
COMPARATORS
11 - 31
11 - 31
11 - 31
Data
Data
ONE
NULL
ZERO
HI-3585
The
32
32
32
5
Figure 2 is a block diagram showing receiver logic.
BIT TIMING
The ARINC 429 specification defines the following timing toler-
ances for received data:
The HI-3585 accepts signals within these tolerances and rejects
signals outside these tolerances. Receiver logic achieves this as
described below:
RECEIVER LOGIC OPERATION
BIT RATE
PULSE RISE TIME
PULSE FALL TIME
PULSE WIDTH
1. An accurate 1MHz clock source is required to validate the
receive signal timing. Less than 0.1% error is recommended.
2. The receiver uses three separate 10-bit sampling shift reg-
isters for Ones detection, Zeros detection and Null detection.
When the input signal is within the differential voltage range
for any shift register’s state (One Zero or Null) sampling
clocks a high bit into that register. When the receive signal is
outside the differential voltage range defined for any shift reg-
ister, a low bit is clocked. Only one shift register can clock a
high bit for any given sample. All three registers clock low
bits if the differential input voltage is between defined state
voltage bands.
Valid data bits require at least three consecutive One or Zero
samples (three high bits) in the upper half of the Ones or
Zeros sampling shift register, and at least three consecutive
Null samples (three high bits) in the lower half of the Null sam-
pling shift register within the data bit interval.
A word gap Null requires at least three consecutive Null sam-
ples (three high bits) in the upper half of the Null sampling
shift register and at least three consecutive Null samples
(three high bits) in the lower half of the Null sampling shift reg-
ister. This guarantees the minimum pulse width.
3. To validate the receive data bit rate, each bit must follow
its preceding bit by not less than 8 samples and not more
than 12 samples. With exactly 1MHz input clock frequency,
the acceptable data bit rates are:
4. Following the last data bit of a valid reception, the Word
Gap timer samples the Null shift register every 10 input
clocks (every 80 clocks for low speed). If a Null is present,
the Word Gap counter is incremented. A Word Gap count of
3 enables the next reception.
DATA BIT RATE MAX
DATA BIT RATE MIN
100K BPS ± 1%
1.5 ± 0.5 µsec
1.5 ± 0.5 µsec
HIGH SPEED
5 µsec ± 5%
HIGH SPEED
125K BPS
83K BPS
34.5 to 41.7 µsec
12K -14.5K BPS
LOW SPEED
10 ± 5 µsec
10 ± 5 µsec
LOW SPEED
10.4K BPS
15.6K BPS