hi-3585 Holt Integrated Circuits, Inc., hi-3585 Datasheet - Page 8

• Manufacturer Part Number: hi-3585
• Description: Terminal Ic With Spi Interface
• Manufacturer: Holt Integrated Circuits, Inc.

FUNCTIONAL DESCRIPTION (cont.)
DATA TRANSMISSION
If Control Register bit CR13 equals “1”, ARINC 429 data is
transmitted immediately following the
instruction that loaded data into the Transmit FIFO. Loading
Control Register bit CR13 to “0” allows the software to control
transmission timing; each time an SPI op code 12 hex is executed,
all loaded Transmit FIFO words are transmitted. If new words are
loaded into the Transmit FIFO before transmission stops, the new
words will also be output. Once the Transmit FIFO is empty and
transmission of the last word is complete, the FIFO can be loaded
with new data which is held until the next SPI 12 hex instruction is
executed. Once transmission is enabled, the FIFO positions are
incremented with the top register loading into the data transmission
shift register. Within 2.5 data clocks the first data bit appears at
AOUT and BOUT. The 31 or 32 bits in the data transmission shift
register are presented sequentially to the outputs in the ARINC 429
format with the following timing:
The word counter detects when all loaded positions have been
transmitted and sets the transmitter ready flag, SR3, high.
TRANSMITTER PARITY
The parity generator counts the Ones in the 31-bit word. If control
register bit CR9 is set to a “0”, the 32nd bit transmitted will make
parity odd. If the control bit is a “1”, the parity is even. Setting CR3
to “0” bypasses the parity generator, and allows 32 bits of data to be
transmitted.
SELF TEST
If Control Register bits CR5 and CR12 equal ”0”, the transmitter
serial output data is internally looped-back into the receiver. Data
passes unmodified from transmitter to receiver. Setting Control
register bit CR12 to ”1” forces AOUT and BOUT to the Null state
regardless of CR5 state.
SYSTEM OPERATION
The receiver is independent of the transmitter. Therefore, control
of data exchanges is strictly at the option of the user. The only
restrictions are:
LINE DRIVER OPERATION
The line driver in the HI-3585 directly drives the ARINC 429 bus.
The two ARINC outputs (AOUT37 and BOUT37) provide a
differential voltage to produce a +10V One, a -10V Zero, and a
0 Volt Null. Control Register bit CR10 controls both the transmitter
data rate and the slope of the differential output signal.
additional hardware is required to control the slope.
ARINC DATA BIT TIME
1. The received data will be overwritten if the Receive FIFO is
full and at least one location is not retrieved before the next
complete ARINC word is received.
2. The Transmit FIFO can store 32 words maximum and
ignores attempts to load additional data when full.
WORD GAP TIME
NULL BIT TIME
DATA BIT TIME
HIGH SPEED
10 Clocks
40 Clocks
5 Clocks
5 Clocks
CS
rising edge of the SPI
LOW SPEED
HOLT INTEGRATED CIRCUITS
320 Clocks
80 Clocks
40 Clocks
40 Clocks
HI-3585
No
8
Transmit timing is derived from a 1 MHZ reference clock. Control
Register bit CR1 determines the reference clock source. If CR1
equals ”0,” a 50% duty cycle 1 MHZ clock should be applied to the
ACLK input pin. If CR1 equals ”1,” the ACLK input is divided to
generate the 1 MHZ ARINC clock. SPI op code 07 hex provides
the HI-3585 with the correct division ratio to generate a 1 MHZ
reference from ACLK.
Loading Control Register bit CR10 to “0” causes a 100 Kbit/s data
rate and a slope of 1.5 µs on the ARINC outputs. Loading CR10 to
“1” causes a 12.5 Kbit/s data rate and a slope of 10 µs. Timing is
set by an on-chip resistor and capacitor and tested to be within
ARINC 429 requirements.
LINE DRIVER OUTPUT PINS
The HI-3585 AOUT37 and BOUT37 pins have 37.5 Ohms in
series with each line driver output, and may be directly connected
to an ARINC 429 bus. The alternate AOUT27 and BOUT27 pins
have 27 ohms of internal series resistance and require external 10
ohm resistors at each pin.
applications where external series resistance is applied, typically
for lightning protection devices.
LINE RECEIVER INPUT PINS
The HI-3585 has two sets of Line Receiver input pins, RINA/B
and RINA/B-40. Only one pair may be used to connect to the
ARINC 429 bus. The unused pair must be left floating. The
RINA/B pins may be connected directly to the ARINC 429 bus.
The RINA/B-40 pins require external 40K ohm resistors in series
with each ARINC input. These do not affect the ARINC receiver
thresholds. By keeping excessive voltage outside the device, this
option is helpful in applications where lightning protection is re-
quired.
When using the RINA/B-40 pins, each side of the ARINC bus
must be connected through a 40K ohm series resistor in order for
the chip to detect the correct ARINC levels. The typical 10 Volt dif-
ferential signal is translated and input to a window comparator
and latch. The comparator levels are set so that with the external
40K ohm resistors, they are just below the standard 6.5 volt mini-
mum ARINC data threshold and just above the standard 2.5 volt
maximum ARINC null threshold.
Please refer to the Holt AN-300 Application Note for additional
information and recommendations on lightning protection of Holt
line drivers and line receivers.
POWER SUPPLY SEQUENCING
Power supply sequencing should be controlled to prevent large
currents during supply turn-on and turn-off. The recommended
sequence is V+ followed by V
most positive supply. The V- supply is not critical and can be
applied at any time.
MASTER RESET (MR)
Application of a Master Reset causes immediate termination of
data transmission and data reception. The transmit and receive
FIFOs are cleared. Status Register FIFO flags and FIFO status
output signals RFLAG and TFLAG are also cleared. The Control
Register is not affected by a Master Reset.
DD
AOUT27 and BOUT27 are for
, always ensuring that V+ is the