s71jl064ha0bfw62 Advanced Micro Devices, s71jl064ha0bfw62 Datasheet - Page 45

• Manufacturer Part Number: s71jl064ha0bfw62
• Description: Stacked Multi-chip Product Mcp Flash Memory And Psram Cmos 3.0volt-only, Simultaneous Operation Flash Memories And Static Ram/pseudo-static Ram
• Manufacturer: Advanced Micro Devices

February 25, 2004 S71JLxxxHxx_00A1
RESET#: Hardware Reset Pin
Output Disable Mode
trol signals. Standard address access timings provide new data when addresses
are changed. While in sleep mode, output data is latched and always available to
the system. I
automatic sleep mode current specification.
The RESET# pin provides a hardware method of resetting the device to reading
array data. When the RESET# pin is driven low for at least a period of t
device immediately terminates any operation in progress, tristates all output
pins, and ignores all read/write commands for the duration of the RESET# pulse.
The device also resets the internal state machine to reading array data. The op-
eration that was interrupted should be reinitiated once the device is ready to
accept another command sequence, to ensure data integrity.
Current is reduced for the duration of the RESET# pulse. When RESET# is held
at V
at V
The RESET# pin may be tied to the system reset circuitry. A system reset would
thus also reset the Flash memory, enabling the system to read the boot-up firm-
ware from the Flash memory.
If RESET# is asserted during a program or erase operation, the RY/BY# pin re-
mains a “0” (busy) until the internal reset operation is complete, which requires
a time of t
BY# to determine whether the reset operation is complete. If RESET# is asserted
when a program or erase operation is not executing (RY/BY# pin is “1”), the reset
operation is completed within a time of t
The system can read data t
Refer to the
for the timing diagram.
When the OE# input is at V
are placed in the high impedance state.
IL
SS
±0.3 V, the device draws CMOS standby current (I
but not within V
READY
"AC
CC5
(during Embedded Algorithms). The system can thus monitor RY/
Characteristics" section tables for RESET# parameters and to
in the
P r e l i m i n a r y
SS
±0.3 V, the standby current will be greater.
"DC
IH
RH
, output from the device is disabled. The output pins
after the RESET# pin returns to V
Characteristics" section table represents the
S29JL064H
READY
(not during Embedded Algorithms).
CC4
). If RESET# is held
IH
.
RP
, the
15
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