s71jl064ha0bfw62 Advanced Micro Devices, s71jl064ha0bfw62 Datasheet - Page 67

• Manufacturer Part Number: s71jl064ha0bfw62
• Description: Stacked Multi-chip Product Mcp Flash Memory And Psram Cmos 3.0volt-only, Simultaneous Operation Flash Memories And Static Ram/pseudo-static Ram
• Manufacturer: Advanced Micro Devices

P r e l i m i n a r y
an address within any of the sectors selected for erasure to read valid status in-
formation on DQ7.
After an erase command sequence is written, if all sectors selected for erasing
are protected, Data# Polling on DQ7 is active for approximately 100 µs, then the
bank returns to the read mode. If not all selected sectors are protected, the Em-
bedded Erase algorithm erases the unprotected sectors, and ignores the selected
sectors that are protected. However, if the system reads DQ7 at an address within
a protected sector, the status may not be valid.
When the system detects DQ7 has changed from the complement to true data,
it can read valid data at DQ15–DQ0 (or DQ7–DQ0 for x8-only device) on the fol-
lowing read cycles. Just prior to the completion of an Embedded Program or Erase
operation, DQ7 may change asynchronously with DQ15–DQ8 (DQ7–DQ0 for x8-
only device) while Output Enable (OE#) is asserted low. That is, the device may
change from providing status information to valid data on DQ7. Depending on
when the system samples the DQ7 output, it may read the status or valid data.
Even if the device has completed the program or erase operation and DQ7 has
valid data, the data outputs on DQ15–DQ0 may be still invalid. Valid data on
DQ15–DQ0 (or DQ7–DQ0 for x8-only device) will appear on successive read
cycles.
Table 12
shows the outputs for Data# Polling on DQ7.
6
shows the Data# Polling
algorithm.
22
in the
"AC
Characteristics" section shows the Data# Polling timing
diagram.
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