kfm2g16q2a-deb8 Samsung Semiconductor, Inc., kfm2g16q2a-deb8 Datasheet - Page 75
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kfm2g16q2a-deb8
Manufacturer Part Number
kfm2g16q2a-deb8
Description
2gb Muxonenand A-die
Manufacturer
Samsung Semiconductor, Inc.
Datasheet
1.KFM2G16Q2A-DEB8.pdf
(173 pages)
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2.8.22 Interrupt Status Register F241h (R/W)
This Read/Write register shows status of the MuxOneNAND interrupts.
In DDP, INT register will not be written if DFS is not set.
F241h, defaults = 8080h after Cold Reset; 8010h after Warm/Hot Reset
Interrupt (INT)
This is the master interrupt bit. The INT bit is wired directly to the INT pin on the chip. Upon writing '0' to the INT bit, the INT pin goes low if
INTpol is high and goes high if INTpol is low.
INT Interrupt [15]
Read Interrupt (RI)
This is the Read interrupt bit.
RI Interrupt [7]
MuxOneNAND2G(KFM2G16Q2A-DEBx)
MuxOneNAND4G(KFN4G16Q2A-DEBx)
INT
15
sets itself to ‘1’
sets itself to ‘1’
clears to ‘0’
clears to ‘0’
Status
Status
14
13
One or more of RI, WI, RSTI and EI is set to ‘1’, or
command is written to Command Register in INT
command is written to Command Register in INT
0065h, 0023h, 0071h, 002Ah, 0027h and 002Ch
Cold/Warm/Hot reset is being performed, or
Cold/Warm/Hot reset is being performed, or
At the completion of an Load Operation
12
Reserved(0000000)
(0000h, 000Eh, 000Ch, 000Ah, 0013h,
Load Data into Buffer, or boot is done)
commands are completed.
’0’ is written to this bit,
’0’ is written to this bit,
11
Conditions
Conditions
auto mode
auto mode
10
9
8
- 75 -
RI
7
Cold
Cold
1
1
WI
Default State
Default State
6
EI
Warm/hot
Warm/hot
5
1
0
RSTI
4
3
Valid
State
State
0
1
Valid
0
1
FLASH MEMORY
→
→
→
→
0
0
1
0
1
0
Reserved(0000)
2
1
Function
Interrupt
Function
Interrupt
Pending
Pending
off
off
off
off
0
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