54abt16952 Fairchild Semiconductor, 54abt16952 Datasheet
54abt16952
Related parts for 54abt16952
54abt16952 Summary of contents
Page 1
... L LOW Voltage Level LOW-to-HIGH Transition X Immaterial NC No Change © 1999 Fairchild Semiconductor Corporation Features Separate clock, clock enable and 3-STATE output enable provided for each register A and B output sink capability source capability Guaranteed latchup protection High impedance glitch free bus loading during entire ...
Page 2
Block Diagram n for either byte 1 or byte 2 www.fairchildsemi.com 2 ...
Page 3
Absolute Maximum Ratings Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias V Pin Potential to CC Ground Pin Input Voltage (Note 2) Input Current (Note 2) Voltage Applied to Any Output in the Disable or Power-Off State in ...
Page 4
AC Electrical Characteristics (SSOP Package) Symbol Parameter f Max Clock max Frequency t Propagation Delay PLH t CPAB or CPBA to PHL Output Enable Time PZH t OEAB or OEBA to PZL ...
Page 5
AC Loading *Includes jig and probe capacitance FIGURE 1. Standard AC Test Load Amplitude 3.0V FIGURE 3. Input Signal Requirements AC Waveforms FIGURE 4. Propagation Delay Waveforms for Inverting and Non-Inverting Functions FIGURE 5. Propagation Delay, Pulse Width Waveforms FIGURE ...
Page 6
Physical Dimensions inches (millimeters) unless otherwise noted 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide www.fairchildsemi.com Package Number MS56A 6 ...
Page 7
Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE ...