cx29600 Mindspeed Technologies, cx29600 Datasheet - Page 134

• Manufacturer Part Number: cx29600
• Description: Optiphytm - M155 Sts-3 Sonet/sdh Multiplexer
• Manufacturer: Mindspeed Technologies

4.0 Registers
4.1 Memory Map
GEN (General Control Register)
The GEN register controls the receiver hold input pin, one-second latch enables, block mode error counting,
status pin selection, and device reset.
4-28
NOTE(S):
(1)
This is only valid when mapping the payload in SDH and AU-4 modes.
Bit
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
hex address: 0x000
MasterReset
LogicReset
CDRReset
AU4Mode
FrmMode
TU3Mode
EnIntPin
Mindspeed Technologies
Name
—
Reserved, set to zero.
When written to 0, the mode of operation is SONET. When written
to 1, the mode of operation is SDH. This mode only affects Z0
insertion.
When written to 0, the payload mapping is via AU-3. When written
to 1, the payload mapping is via AU-4.
When written to 1, the interrupt output pin Mint* is enabled. When
written to 0, the interrupt output is three-stated.
When written to 0, the payload mapping is via TUG-2. When
written to 1, the payload mapping is via TU-3.
Active high reset control to the CDR. Since the CDR is not reset by
the chip reset pin, use this register to reset the CDR.
When written to 1, all internal state machines are held in reset
mode but register contents are not affected.
When written to 1, all internal state machines are held in reset
mode AND all control registers are set to their default values
(except bit 0 in this register).
™
Description
CX29600 Data Sheet
1
29600-DSH-001-B
CX29600