cx29600 Mindspeed Technologies, cx29600 Datasheet - Page 94
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cx29600
Manufacturer Part Number
cx29600
Description
Optiphytm - M155 Sts-3 Sonet/sdh Multiplexer
Manufacturer
Mindspeed Technologies
Datasheet
1.CX29600.pdf
(219 pages)
- Current page: 94 of 219
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2.0 Functional Description
2.7 TTL/PECL Interface
2.7.1 PECL Bias Network
Figure 2-24. PECL Bias Network
2-50
Output+
Output–
The CX29600 can utilize a new PECL bias network as shown in
This simplifies board layout by eliminating the pull-up resistors used in previous
PECL interfaces. The CX29600 is backward compatible with legacy layouts as
shown in
high-speed practices must be followed:
where:
Using the generic values Z
width (w) of 0.11 inches.
All PECL traces must be treated as transmission lines. Therefore, standard
• Keep traces as short as reasonable.
• Do not allow traces to cross discontinuities in the ground/power planes.
• Use separate Power and Ground planes.
• Terminate all inputs and outputs as described above.
• Place the terminating resistors as close to the destination IC as possible.
• Do not route signal traces through the board through vias.
• Check that each IC has two high-quality RF bypass capacitors that are at
• Avoid 90 degree turns in trace routing.
• Ensure that the trace width results in a line impedance that matches the
w = trace width
Z
h = board thickness (not including copper layers)
t = thickness of copper layers
e
r
0
= relative dielectric constant of the board
= characteristic line impedance
least an order of magnitude apart; e.g., 200 pF and 0.1 µF.
input impedance of the load. Trace width can be calculated from the
following equation:
Mindspeed Technologies
Appendix
130
A.
w
=
130
⎛
⎜
⎝
7.745
0
100
= 50 Ω, h = 0.060, t = 0.0015 and e
×
h
×
e
–
™
--------------------------------------
e
Input+
Input–
r
+
1.41
87
×
Z 0
⎞
⎟
⎠
–
------ -
0.8
t
100518_032
CX29600 Data Sheet
29600-DSH-001-B
r
= 4.8 results in a
Figure
2-24.
CX29600
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