cx29600 Mindspeed Technologies, cx29600 Datasheet - Page 162

• Manufacturer Part Number: cx29600
• Description: Optiphytm - M155 Sts-3 Sonet/sdh Multiplexer
• Manufacturer: Mindspeed Technologies

4.0 Registers
4.1 Memory Map
SUMINT (Summary Interrupt Indication Register)
The SUMINT register indicates data link interrupts, one-second interrupts, and additional summary interrupts.
TESTMODE (Test Mode Control Register)
The TESTMODE register controls various circuits of the device. The most important one is the Speed_CP bit
which controls the receive CDR charge pump frequency. This bit must be set to the correct mode for proper
device operation.
4-56
(1)
Reading this register clears the interrupt indication.
Bit
7
6
5
4
3
2
1
0
7-6
Bit
5
4
3
2
1
0
Default
0
0
1
0
0
0
0
0
Default
00
—
—
—
x
x
x
SDCC_Loopback_mode
LDCC_loopback_mode
E1E2_Loopback_mode
hex address: 0x005
hex address: 0x007
SONET_Bypass
RxLosAllOnes
Speed_CP
Pd_TxSyn
Name
—
OneSecInt
PLLRefInt
Mindspeed Technologies
Port1Int
Name
—
—
—
—
1
Reserved, set to zero.
PLL Reference has occurred.
This bit indicates that a one-second interrupt has occurred.
Reserved.
Reserved.
Reserved.
This bit indicates that an interrupt has occurred in a Port 1
interrupt register.
CDR charge pump frequency select
0—155 (250 µA). Set to 0 for 4xOC-3 mode.
1—622 (1 mA). Set to 1 for 1xOC-12 mode.
When written to 1, powerdown transmit synthesizer.
When written to 1, LOS is genererated when 100us of all ones is
Bypasses the SONET transmission/reception used to debug and
test the CDR block.
Line DCC internal reception-to-transmission loopback.
Section DCC internal reception-to-transmission loopback.
E1 and E2 orderwire internal transmission-to-reception loopback.
Reserved
received.
™
Description
Description
CX29600 Data Sheet
29600-DSH-001-B
CX29600