lc890561w Sanyo Semiconductor Corporation, lc890561w Datasheet - Page 15

• Manufacturer Part Number: lc890561w
• Description: Cmos Digital Audio Interface Receiver With Built-in Data Buffer Memory
• Manufacturer: Sanyo Semiconductor Corporation

12.4 Output Clock (CKOUT, BCK, LRCK)
• The CKOUT output clock is selected by setting CKSEL0 and CKSEL1 terminals.
• 256fs must be chosen when receiving data over 96kHz as above table. There is no restriction of selection for data
• 512fs/2 set PLL band as 512fs, and CKOUT clock outputs one half (256fs output).
• 64fs clock (64fs only) is outputted from BCK, and the fs clock is outputted from LRCK.
• When PLL is unlocked, the XIN and XOUT oscillation amplifier clock or the external input clock is output from
• Output of 1/2 CKOUT clock by CKDV command is possible.
• Reverse of the polarity of CKOUT clock by CKPO command is also possible.
• In the PLL lock and unlock phases, the CKOUT (BCK and LRCK likewise) clock switch timing is as follows.
reception under 96kHz.
CKOUT, and the divided clock of this clock is outputted from BCK and LRCK.
PLL lock state
PLL lock state
DIN0 to DIN2
DIN0 to DIN2
VCO clock
(XSTP = 0)
VCO clock
(XSTP = 0)
XIN clock
XIN clock
CKSEL1 pin
XSTATE
XSTATE
ERROR
ERROR
CKOUT
CKOUT
0
0
1
1
Digital data
UNLOCK
Table 12.4 CKOUT Output Clock Selection
LOCK
Figure 12.1 Output Clock Switch Timing
Same
LC890561W
(a): During lock-in phase
(b): During unlock phase
CKSEL0 pin
0
1
0
1
Digital data
1ms to 276ms
5ms to 12ms
LOCK
UNLOCK
512fs/2 output
256fs output
384fs output
512fs output
CKOUT pin
Same
No8226-15/47