lc890561w Sanyo Semiconductor Corporation, lc890561w Datasheet - Page 26

• Manufacturer Part Number: lc890561w
• Description: Cmos Digital Audio Interface Receiver With Built-in Data Buffer Memory
• Manufacturer: Sanyo Semiconductor Corporation

13.2 DATAO Output Data Processing
• When any of the DTMA [4:0], DTMB [3:0], DTMC [2:0], DTMX [4:0], DTMY [3:0] is set up (setup of those other
• Delay processing of the target data and mute processing of output data are explained below.
13.2.1 Output Data Delay Setup after Recovery Processing (Setting at the state of ERROR = H)
• When the DTMA[4:0], DTMB[3:0] and DTMC[2:0] commands are set up or changed during high output of ERROR
• Readout of the data written in the memory is started after the set delay time (frame).
• The data read out is constantly output form DATAO with the delay of the setup time.
• DATAO will be muted until the set delay time is over, because sufficient data is not written into memory immediately
• When the DTMA[4:0], DTMB[3:0] and DTMC[2:0] commands are canceled during high output of ERROR flag, data
than an initial state), delay processing of output data is performed.
flag, data is written into memory in synchronization with the rising edge of XSTATE after PLL is locked.
after the low output of ERROR flag.
is output from DATAO synchronizing with the rising edge of XSTATE after PLL is locked. This is normal operation
which does not perform a delay processing setup.
(XSTP = 0)
Lock state
Figure 13.1 Timing Chart for Output Data after Setup or Change of the Delay Time During PLL Lock-in
DATAO2
XSTATE
(XSTP = 0)
Figure 13.2 Timing Chart for Output Data after Cancel of the Delay Time Setting During PLL Lock-in
ERROR
Lock state
DATAO
DATAO2
XSTATE
ERROR
DIN*
DATAO
DIN*
SDIN data
SDIN data
Unlock
SDIN data
SDIN data
Unlock
Wn-2
Wn-2
Mn-1 Wn-1
Mn-1 Wn-1
3ms to 300ms
Wait period:
3ms to 300ms
Wait period:
LC890561W
M1
0 data (mute)
0 data (mute)
M1
0 data (mute)
0 data (mute)
W1
W1
Same
Same
M2
M2
W2
L0
W2
L0
L0
Lock
M3
R0
Lock
M3
Delay time
R0
R0
Mn+1 Wn+1 Mn+2 Wn+2
Ln
Mn+1 Wn+1 Mn+2 Wn+2
Ln
Ln
Rn
Rn
Rn
Ln+1
L0
Ln+1
Ln+1
Rn+1
R0
Rn+1
Rn+1
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