lc890561w Sanyo Semiconductor Corporation, lc890561w Datasheet - Page 38

• Manufacturer Part Number: lc890561w
• Description: Cmos Digital Audio Interface Receiver With Built-in Data Buffer Memory
• Manufacturer: Sanyo Semiconductor Corporation

DLPO
DOM[1:0]
EWT[1:0]
The pulse width of XSTATE output after a PLL lock by input data is as follows.
DLMP output polarity setting (Enable, when FSEL = 1)
DATAO, DATAO2 mute setting
An ERROR output waiting time setup after a PLL lock
0
1
00
01
10
11
00
01
10
11
Input fs
176.4kHz
XSTATE pulse width = {192/fs × (“EWT[1:0] count value” - 2)}
44.1kHz
88.2kHz
:
:
:
:
:
:
:
:
:
:
192kHz
32kHz
48kHz
96kHz
Normal L output (default)
Normal H output
The data chosen by SMOD is outputted (default)
Only DATAO is muted
Only DATAO2 is muted
DATAO and DATAO2 are muted
Cancel error after preamble B is counted to 48 (default)
Cancel error after preamble B is counted to 12
Cancel error after preamble B is counted to 6
Cancel error after preamble B is counted to 3
LC890561W
“00”
276.0ms
200.2ms
184.0ms
100.1ms
Table 14.3. Pulse Width of XSTATE output
92.0ms
50.0ms
46.0ms
“01”
60.0ms
43.5ms
40.0ms
21.7ms
20.0ms
10.8ms
10.0ms
EWT[1:0]
“10”
24.0ms
17.4ms
16.0ms
8.7ms
8.0ms
4.3ms
4.0ms
“11”
6.0ms
4.3ms
4.0ms
2.1ms
2.0ms
1.0ms
1.0ms
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