lc890561w Sanyo Semiconductor Corporation, lc890561w Datasheet - Page 36

• Manufacturer Part Number: lc890561w
• Description: Cmos Digital Audio Interface Receiver With Built-in Data Buffer Memory
• Manufacturer: Sanyo Semiconductor Corporation

DIS[1:0]
FSL[1:0]
ERF[1:0]
BMOD
CKDV
If set reception range is exceeded, ERROR is output as high even if PLL is locked.
In case ERF[1:0]=00, although no error flag is output, the process for error is executed for
output data.
In case ERF[1:0]=01, no error flag is output when the delay setting of output data is
performed.
In case ERF[1:0]=11, Non-PCM burst data recognition is performed when channel status
bit1 is high.
S/PDIF Input data pin setting
S/PDIF Input data reception range setting
Parity error flag output setting if 8 or fewer input parity errors occur in succession
DOUT output state setting
CKOUT output state setting when PLL is locked
00
01
10
11
00
01
10
11
00
01
10
11
0
1
0
1
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Follow DISEL setting (default)
Select DIN0
Select DIN1
Select DIN2
Normal mode (Same as the mode 1 of MODE0 and MODE1)
(default)
32kHz to 48kHz
Fs free mode A (Same as the mode 2 of MODE0 and MODE1)
32kHz to 96kHz
Error flag is not output (default)
Only output during sub-frame with error
Reserved
Only output upon Non-PCM burst data recognition
Outputs a selected input data (default)
L fixed
Output CKSEL0 and CKSEL1 setting clock (default)
Output 1/2 of CKSEL0 and CKSEL1 setting clock
LC890561W
No8226-36/47